公开(公告)号：US20110147850A1

公开(公告)日：2011-06-23

申请号：US12967109

申请日：2010-12-14

Applicant: Mahalingam Nandakumar ,  Amitabh Jain

Inventor： Mahalingam Nandakumar ,  Amitabh Jain

IPC: H01L27/088 ,  H01L21/336

CPC classification number: H01L21/823412 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/28202 ,  H01L21/823418 ,  H01L21/823462 ,  H01L29/1083 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method of forming an integrated circuit (IC) including a core and a non-core PMOS transistor includes forming a non-core gate structure including a gate electrode on a gate dielectric and a core gate structure including a gate electrode on a gate dielectric. The gate dielectric for the non-core gate structure is at least 2 Å of equivalent oxide thickness (EOT) thicker as compared to the gate dielectric for the core gate structure. P-type lightly doped drain (PLDD) implantation including boron establishes source/drain extension regions in the substrate. The PLDD implantation includes selective co-implanting of carbon and nitrogen into the source/drain extension region of the non-core gate structure. Source and drain implantation forms source/drain regions for the non-core and core gate structure, wherein the source/drain regions are distanced from the non-core and core gate structures further than their source/drain extension regions. Source/drain annealing is performed after source and drain implantation.

Abstract translation: 形成包括芯和非芯型PMOS晶体管的集成电路（IC）的方法包括在栅极电介质上形成包括栅电极的非核栅极结构和在栅极电介质上包括栅电极的芯栅极结构。 与核心栅极结构的栅极电介质相比，非核心栅极结构的栅极电介质至少为等效氧化物厚度（EOT）的2埃。 包括硼的P型轻掺杂漏极（PLDD）注入在衬底中建立源极/漏极延伸区域。 PLDD注入包括将碳和氮选择性共注入到非核栅极结构的源极/漏极延伸区域中。 源极和漏极注入形成用于非核和核栅极结构的源极/漏极区，其中源极/漏极区远离它们的源极/漏极延伸区域的非核心和核栅极结构。 在源极和漏极之间进行源极/漏极退火。

公开(公告)号：US20110133287A1

公开(公告)日：2011-06-09

申请号：US13016393

申请日：2011-01-28

Applicant: Amitabh Jain

Inventor： Amitabh Jain

IPC: H01L27/088

CPC classification number: H01L21/26506 ,  H01L21/02667 ,  H01L21/02675 ,  H01L21/26593 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/7848

Abstract: An integrated circuit (IC) includes a plurality of compressively strained PMOS transistors. The IC includes a substrate having a semiconductor surface. A gate stack is formed in or on the semiconductor surface and includes a gate electrode on a gate dielectric, wherein a channel region is located in the semiconductor surface below the gate dielectric. A source and a drain region is opposing sides of the gate stack. At least one compressive strain inducing region including at least one specie selected from Ge, Sn and Pb is located in at least a portion of the source and drain regions of the PMOS transistors, wherein the strain inducing region provides ≦1010 dislocation lines/cm2 and an active concentration of the compressive strain inducing specie that is above a solid solubility limit for the compressive strain inducing specie in the compressive strain inducing region. A method for forming compressively strained PMOS transistors includes implanting on at least opposing sides of the gate stack using at least one compressive strain inducing specie selected from Ge, Sn and Pb at a dose ≧1×1015cm−2, at an implantation temperature during implanting in a temperature range ≦273 K, wherein the implant conditions are sufficient to form an amorphous region. The wafer is annealed using annealing conditions including a peak anneal temperature of between 1050° C. and 1400° C. and an anneal time at the peak temperature of ≦10 seconds, wherein the amorphous region recrystallizes by solid phase epitaxy (SPE).

Abstract translation: 集成电路（IC）包括多个压缩应变PMOS晶体管。 IC包括具有半导体表面的衬底。 栅堆叠形成在半导体表面中或半导体表面上，并且在栅极电介质上包括栅电极，其中沟道区位于栅电介质下方的半导体表面中。 源极和漏极区域是栅极堆叠的相对侧。 包括至少一种选自Ge，Sn和Pb的物质的至少一个压缩应变诱导区域位于PMOS晶体管的源极和漏极区域的至少一部分中，其中应变诱导区域提供1010个位错线/ cm 2 以及压缩应变诱导物质的活性浓度高于在压缩应变诱导区域中的压缩应变诱导物质的固溶度极限。 用于形成压缩应变PMOS晶体管的方法包括：在植入期间的植入温度下，使用至少一种压应变诱导物种，以剂量≥1×1015cm-2的剂量从Ge，Sn和Pb中选出的至少一个压电应变诱导栅叠层的至少相对侧进行注入 在温度范围＆amp; 273; K K，其中注入条件足以形成无定形区域。 使用包括1050℃至1400℃的峰退火温度和在峰值温度为＆lt; lE; 10秒的退火时间的退火条件对晶片进行退火，其中非晶区域通过固相外延（SPE）重结晶。

公开(公告)号：US07932139B2

公开(公告)日：2011-04-26

申请号：US11743440

申请日：2007-05-02

Applicant: Haowen Bu ,  Amitabh Jain

Inventor： Haowen Bu ,  Amitabh Jain

IPC: H01L21/268 ,  B23K26/00

CPC classification number: C21D1/26 ,  B23K26/0853 ,  B23K2101/40 ,  C21D9/50

Abstract: A method of laser annealing a workpiece for reduction of warpage, slip defects and breakage, the method comprising (a) moving a workpiece through a laser beam in a x-axis first direction, (b) moving the workpiece in a y-axis second direction, (c) moving the workpiece through a laser beam in a minus x-axis first direction and repeating (a)-(c) until the workpiece is fully annealed in two successive laser annealing iterations.

Abstract translation: 一种对工件进行激光退火以减少翘曲，滑动缺陷和断裂的方法，所述方法包括：（a）沿x轴第一方向移动通过激光束的工件，（b）在y轴第二方向上移动工件 方向，（c）通过激光束沿负x轴第一方向移动工件，并重复（a） - （c），直到工件在两次连续的激光退火迭代中完全退火。

公开(公告)号：US07902032B2

公开(公告)日：2011-03-08

申请号：US12345851

申请日：2008-12-30

Applicant: Amitabh Jain

Inventor： Amitabh Jain

IPC: H01L21/336

CPC classification number: H01L21/26506 ,  H01L21/02667 ,  H01L21/02675 ,  H01L21/26593 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/7848

Abstract: An integrated circuit (IC) includes a plurality of compressively strained PMOS transistors. The IC includes a substrate having a semiconductor surface. A gate stack is formed in or on the semiconductor surface and includes a gate electrode on a gate dielectric, wherein a channel region is located in the semiconductor surface below the gate dielectric. A source and a drain region is opposing sides of the gate stack. At least one compressive strain inducing region including at least one specie selected from Ge, Sn and Pb is located in at least a portion of the source and drain regions of the PMOS transistors, wherein the strain inducing region provides ≦1010 dislocation lines/cm2 and an active concentration of the compressive strain inducing specie that is above a solid solubility limit for the compressive strain inducing specie in the compressive strain inducing region. A method for forming compressively strained PMOS transistors includes implanting on at least opposing sides of the gate stack using at least one compressive strain inducing specie selected from Ge, Sn and Pb at a dose ≧1×1015 cm−2, at an implantation temperature during implanting in a temperature range ≦273 K, wherein the implant conditions are sufficient to form an amorphous region. The wafer is annealed using annealing conditions including a peak anneal temperature of between 1050° C. and 1400° C. and an anneal time at the peak temperature of ≦10 seconds, wherein the amorphous region recrystallizes by solid phase epitaxy (SPE).

Abstract translation: 集成电路（IC）包括多个压缩应变PMOS晶体管。 IC包括具有半导体表面的衬底。 栅堆叠形成在半导体表面中或半导体表面上，并且在栅极电介质上包括栅电极，其中沟道区位于栅电介质下方的半导体表面中。 源极和漏极区域是栅极堆叠的相对侧。 包括至少一种选自Ge，Sn和Pb的物质的至少一个压缩应变诱导区域位于PMOS晶体管的源极和漏极区域的至少一部分中，其中应变诱导区域提供1010个位错线/ cm 2 以及压缩应变诱导物质的活性浓度高于在压缩应变诱导区域中的压缩应变诱导物质的固溶度极限。 用于形成压缩应变PMOS晶体管的方法包括：在植入温度期间，使用至少一种压应变诱导物质，以剂量≥1×1015cm-2，在栅极堆叠的至少相对侧上注入; 在温度范围内注入; 273K，其中注入条件足以形成非晶区域。 使用包括1050℃至1400℃的峰退火温度和在峰值温度为＆lt; lE; 10秒的退火时间的退火条件对晶片进行退火，其中非晶区域通过固相外延（SPE）重结晶。

公开(公告)号：US20110042753A1

公开(公告)日：2011-02-24

申请号：US12855736

申请日：2010-08-13

Applicant: Amitabh Jain ,  Deborah J. Riley

Inventor： Amitabh Jain ,  Deborah J. Riley

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L29/7848

Abstract: An integrated circuit (IC) includes a plurality of strained metal oxide semiconductor (MOS) devices that include a semiconductor surface having a first doping type, a gate electrode stack over a portion of the semiconductor surface, and source/drain recesses that extend into the semiconductor surface and are framed by semiconductor surface interface regions on opposing sides of the gate stack. A first epitaxial strained alloy layer (rim) is on the semiconductor surface interface regions, and is doped with the first doping type. A second epitaxial strained alloy layer is on the rim and is doped with a second doping type that is opposite to the first doping type that is used to form source/drain regions.

Abstract translation: 集成电路（IC）包括多个应变金属氧化物半导体（MOS）器件，其包括具有第一掺杂类型的半导体表面，半导体表面的一部分上的栅极电极堆叠以及延伸到 半导体表面并且由栅堆叠的相对侧上的半导体表面界面区域构成。 第一外延应变合金层（边缘）在半导体表面界面区域上，并掺杂有第一掺杂型。 第二外延应变合金层位于边缘上并且掺杂有与用于形成源极/漏极区的第一掺杂类型相反的第二掺杂类型。

公开(公告)号：US07666748B2

公开(公告)日：2010-02-23

申请号：US11614300

申请日：2006-12-21

Applicant: Amitabh Jain

Inventor： Amitabh Jain

IPC: H01L21/336

CPC classification number: H01L29/66636 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for making a transistor within a semiconductor wafer. The method may include etching a recess at source/drain extension locations and depositing amorphous silicon within the recess to from amorphous silicon source/drain extensions. Dopants may be implanted into the amorphous silicon source/drain extensions and the semiconductor wafer may then be annealed.

Abstract translation: 一种在半导体晶片内制造晶体管的方法。 该方法可以包括蚀刻源极/漏极延伸位置处的凹部并且在凹陷内从非晶硅源极/漏极延伸部分沉积非晶硅。 可以将掺杂剂注入到非晶硅源极/漏极延伸部分中，然后可以将半导体晶片退火。

公开(公告)号：US20090184375A1

公开(公告)日：2009-07-23

申请号：US12345851

申请日：2008-12-30

Applicant: Amitabh Jain

Inventor： Amitabh Jain

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/26506 ,  H01L21/02667 ,  H01L21/02675 ,  H01L21/26593 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/7848

Abstract: An integrated circuit (IC) includes a plurality of compressively strained PMOS transistors. The IC includes a substrate having a semiconductor surface. A gate stack is formed in or on the semiconductor surface and includes a gate electrode on a gate dielectric, wherein a channel region is located in the semiconductor surface below the gate dielectric. A source and a drain region is opposing sides of the gate stack. At least one compressive strain inducing region including at least one specie selected from Ge, Sn and Pb is located in at least a portion of the source and drain regions of the PMOS transistors, wherein the strain inducing region provides ≦1010 dislocation lines/cm2 and an active concentration of the compressive strain inducing specie that is above a solid solubility limit for the compressive strain inducing specie in the compressive strain inducing region. A method for forming compressively strained PMOS transistors includes implanting on at least opposing sides of the gate stack using at least one compressive strain inducing specie selected from Ge, Sn and Pb at a dose ≧1×1015 cm−2, at an implantation temperature during implanting in a temperature range ≦273 K, wherein the implant conditions are sufficient to form an amorphous region. The wafer is annealed using annealing conditions including a peak anneal temperature of between 1050° C. and 1400° C. and an anneal time at the peak temperature of ≦10 seconds, wherein the amorphous region recrystallizes by solid phase epitaxy (SPE).

Abstract translation: 集成电路（IC）包括多个压缩应变PMOS晶体管。 IC包括具有半导体表面的衬底。 栅堆叠形成在半导体表面中或半导体表面上，并且在栅极电介质上包括栅电极，其中沟道区位于栅电介质下方的半导体表面中。 源极和漏极区域是栅极堆叠的相对侧。 包括至少一种选自Ge，Sn和Pb的物质的至少一个压缩应变诱导区位于PMOS晶体管的源区和漏区的至少一部分中，其中应变诱导区提供<= 1010位错线/ cm2 以及压缩应变诱导物质的活性浓度高于在压缩应变诱导区域中的压缩应变诱导物质的固溶度极限。 用于形成压缩应变PMOS晶体管的方法包括：在植入期间的注入温度下，使用至少一种压应变诱导物种，以剂量≥1×10 15 cm -2的剂量从Ge，Sn和Pb中选出的至少一个压电应变诱导栅堆叠的至少相对侧进行注入 在<= 273K的温度范围内，其中注入条件足以形成非晶区域。 使用包括1050℃至1400℃的峰退火温度和峰值温度<= 10秒的退火时间的退火条件对晶片进行退火，其中非晶区域通过固相外延（SPE）重结晶。

公开(公告)号：US07557021B2

公开(公告)日：2009-07-07

申请号：US11175682

申请日：2005-07-06

Applicant: Amitabh Jain

Inventor： Amitabh Jain

IPC: H01L21/265

CPC classification number: H01L21/2807

Abstract: The present invention provides, in one embodiment, a method for fabricating a microelectronic device. The method comprises implanting a dopant into a gate electrode located on a substrate. The gate electrode has a melting point below a melting point of the substrate. The method also comprises melting the gate electrode to allow the dopant to diffuse throughout the gate electrode. The method further comprises re-solidifying the gate electrode to increase dopant-occupied substitutional sites within the gate electrode.

Abstract translation: 在一个实施例中，本发明提供了一种用于制造微电子器件的方法。 该方法包括将掺杂剂注入到位于衬底上的栅电极中。 栅电极的熔点低于基板的熔点。 该方法还包括熔化栅电极以允许掺杂剂在整个栅电极中扩散。 该方法还包括重新固化栅电极以增加栅电极内的掺杂剂占据的取代位置。

公开(公告)号：US20090079008A1

公开(公告)日：2009-03-26

申请号：US12209270

申请日：2008-09-12

Applicant: Mahalingam Nandakumar ,  Song Zhao ,  Amitabh Jain

Inventor： Mahalingam Nandakumar ,  Song Zhao ,  Amitabh Jain

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823814 ,  H01L29/1087 ,  H01L29/7847

Abstract: Ultra high temperature (UHT) anneals above 1200 C for less than 100 milliseconds for PMOS transistors reduce end of range dislocations, but are incompatible with stress memorization technique (SMT) layers used to enhance NMOS on-state current. This invention reverses the conventional order of forming the NMOS first by forming PSD using carbon co-implants and UHT annealing them before implanting the NSD and depositing the SMT layer. End of range dislocation densities in the PSD space charge region below 100 cm−2 are achieved. Tensile stress in the PMOS from the SMT layer is significantly reduced. The PLDD may also be UHT annealed to reduce end of range dislocations close to the PMOS channel.

Abstract translation: 对于PMOS晶体管，超高温（UHT）超过1200℃退火少于100毫秒会减少范围位错的终止，但与用于增强NMOS导通电流的应力记忆技术（SMT）层不兼容。 本发明首先通过使用碳共注入形成PSD并且在植入NSD并沉积SMT层之前对其进行UHT退火来逆转形成NMOS的常规顺序。 实现了低于100cm-2的PSD空间电荷区域的范围位错密度的结束。 来自SMT层的PMOS中的拉伸应力显着降低。 PLDD还可以进行UHT退火以减少靠近PMOS沟道的范围位错的结束。

公开(公告)号：US07494905B2

公开(公告)日：2009-02-24

申请号：US10920023

申请日：2004-08-17

Applicant: Amitabh Jain

Inventor： Amitabh Jain

IPC: H01L21/04 ,  H01L21/26 ,  H01L21/42

CPC classification number: H01J37/08 ,  H01J2237/31701 ,  H01L21/26513 ,  H01L21/2658 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present invention provides, for use in a semiconductor manufacturing process, a method (100) of preparing an ion-implantation source material. The method includes providing (110) a deliquescent ion implantation source material and mixing (110) the deliquescent ion implantation source material with an organic liquid to form a paste.

Abstract translation: 为了在半导体制造工艺中使用本发明，提供了制备离子注入源材料的方法（100）。 该方法包括提供（110）潮解离子注入源材料，并将潮解离子注入源材料与有机液体混合（110）以形成糊状物。