公开(公告)号：US07462512B2

公开(公告)日：2008-12-09

申请号：US11033046

申请日：2005-01-11

申请人： Kalle Levon ,  Arifur Rahman ,  Tsunehiro Sai ,  Ben Zhao

发明人： Kalle Levon ,  Arifur Rahman ,  Tsunehiro Sai ,  Ben Zhao

IPC分类号： H01L21/00

CPC分类号： G01N27/4145 ,  G01N27/4148

摘要： Specific ionic interactions with a sensing material that is electrically coupled with the floating gate of a floating gate-based ion sensitive field effect transistor (FGISFET) may be used to sense a target material. For example, an FGISFET can use (e.g., previously demonstrated) ionic interaction-based sensing techniques with the floating gate of floating gate field effect transistors. The floating gate can serves as a probe and an interface to convert chemical and/or biological signals to electrical signals, which can be measured by monitoring the change in the device's threshold voltage, VT.

摘要翻译： 可以使用与浮置栅极离子敏感场效应晶体管（FGISFET）的浮动栅极电耦合的感测材料的特定离子相互作用来感测目标材料。 例如，FGISFET可以使用浮动栅极场效应晶体管的浮动栅极（例如，先前证明的）基于离子相互作用的感测技术。 浮动栅极可以用作探测器和将化学和/或生物信号转换为电信号的接口，这可以通过监测器件的阈值电压VT的变化来测量。

公开(公告)号：US07389485B1

公开(公告)日：2008-06-17

申请号：US11390925

申请日：2006-03-28

申请人： Anirban Rahut ,  Satyaki Das ,  Arifur Rahman

发明人： Anirban Rahut ,  Satyaki Das ,  Arifur Rahman

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/5054 ,  G06F2217/78

摘要： Methods of routing user designs in programmable logic devices (PLDs) having heterogeneous routing structures, i.e., PLDs including both high-power and low-power interconnect resources. A first pass routing step is performance-based, e.g., utilizes a cost function biased towards the high-power interconnect resources. The first routed design is then evaluated to identify non-critical nets in the first routed design that can yield the most power-saving benefit by being retargeted to the low-power interconnect resources. For example, a sorted list of nets can be created in which the identified nets are evaluated based on the capacitance per load pin of each net. A second pass routing step is then performed, e.g., rerouting the nets identified as being non-critical and having the greatest potential power-saving benefit. In some embodiments, the permitted increase in the delay of each rerouted net is bound by the slack of the net as routed in the first routed design.

摘要翻译： 在具有异构路由结构的可编程逻辑设备（PLD）中路由用户设计的方法，即包括大功率和低功率互连资源的PLD。 第一路由路由步骤是基于性能的，例如，利用偏向大功率互连资源的成本函数。 然后评估第一路由设计以识别第一路由设计中的非关键网络，其可以通过重定向到低功率互连资源来产生最节能的优点。 例如，可以创建网络的排序列表，其中基于每个网络的每个负载引脚的电容来评估所识别的网络。 然后执行第二通路由步骤，例如重新路由被识别为非关键并且具有最大潜在省电优点的网络。 在一些实施例中，允许的每个重新路由网络的延迟增加受到在第一路由设计中路由的网络的松弛的约束。

公开(公告)号：US07375546B1

公开(公告)日：2008-05-20

申请号：US11449202

申请日：2006-06-08

申请人： Arifur Rahman

发明人： Arifur Rahman

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/1737 ,  H03K17/005 ,  H03K17/04206 ,  H03K17/6872 ,  H03K17/693 ,  H03K19/00369 ,  H03K2217/0036

摘要： Methods of compensating for power supply variations in an integrated circuit. During operation of the IC die, a power supply voltage level is monitored. When the power supply voltage level drops below a specified level, a performance compensation circuit in the IC is enabled, bringing a first delay (e.g., the rising delay) for a compensated circuit in the IC more closely into alignment with a second delay (e.g., a falling delay) for the circuit. When the power supply voltage level exceeds the specified level, the performance compensation circuit is disabled. When the IC is a programmable IC, for example, the compensated circuit can be a programmable interconnect multiplexer of the programmable IC. In these embodiments, the power supply voltage level for the pass transistors in the interconnect multiplexer can be monitored and compensated for as described above.

摘要翻译： 补偿集成电路电源变化的方法。 在IC管芯工作期间，监视电源电压电平。 当电源电压电平降低到指定电平以下时，IC中的性能补偿电路被使能，使得IC中的补偿电路的第一延迟（例如，上升延迟）更接近地与第二延迟（例如， ，下降延迟）。 当电源电压电平超过指定电平时，性能补偿电路被禁止。 当IC是可编程IC时，例如，补偿电路可以是可编程IC的可编程互连多路复用器。 在这些实施例中，如上所述，可以对互连多路复用器中的传输晶体管的电源电压电平进行监视和补偿。

公开(公告)号：US07370294B1

公开(公告)日：2008-05-06

申请号：US11111652

申请日：2005-04-21

申请人： Arifur Rahman

发明人： Arifur Rahman

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A low-leakage circuit design method involves determining a capacity of a power gating transistor using delay statistics, wherein the resulting power gating transistor has sufficient capacity to supply all of the current necessary to meet the demands of the powered design elements while minimizing an amount of chip space required to implement the power gating transistor. The capacity of the power gating transistor is determined by first estimating a capacity necessary to meet the demands of all design elements connected to the transistor. The design elements are then grouped according to input signal arrival time to determine an amount by which the estimated capacity of the gating transistor may be reduced without affecting operation of the design elements. Various grouping schemes are evaluated to determine an optimal grouping. The estimated transistor capacity is reduced according to the optimal grouping, and the power gating transistor is implemented accordingly.

摘要翻译： 低泄漏电路设计方法包括使用延迟统计来确定功率门控晶体管的容量，其中所得的功率门控晶体管具有足够的容量来提供满足供电设计元件的需求所需的所有电流，同时最小化 实现电源门控晶体管所需的芯片空间。 功率门控晶体管的容量通过首先估计满足连接到晶体管的所有设计元件的需求所需的容量来确定。 然后根据输入信号到达时间对设计元件进行分组，以确定可以在不影响设计元件的操作的情况下降低门控晶体管的估计容量的量。 评估各种分组方案以确定最佳分组。 根据最佳分组，估计晶体管容量减小，相应地实现功率门控晶体管。

公开(公告)号：US07365563B1

公开(公告)日：2008-04-29

申请号：US11449203

申请日：2006-06-08

申请人： Arifur Rahman

发明人： Arifur Rahman

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K19/17764 ,  H03K17/005 ,  H03K17/693 ,  H03K19/00384 ,  H03K19/1778

摘要： Multiplexer circuits that can be programmed to selectively balance the rising and falling delays through the circuits in the presence of process variations and/or variations in power levels. These multiplexer circuits can be used, for example, as programmable interconnect multiplexers in the interconnect structures of programmable logic devices (PLDs). A multiplexer circuit includes a multiplexer (e.g., driven by a plurality of interconnect lines in a PLD), a logic gate (e.g., an inverter) driven by the multiplexer, and a performance compensation circuit. The performance compensation circuit is coupled to the output terminal of the inverter, and has a compensation enable input terminal. The performance compensation circuit is coupled to adjust a trip point of the logic gate based on a value of a signal provided on the compensation enable input terminal.

摘要翻译： 可以编程的多路复用器电路在存在过程变化和/或功率电平变化的情况下选择性地平衡通过电路的上升和下降延迟。 这些多路复用器电路可以例如用作可编程逻辑器件（PLD）的互连结构中的可编程互连多路复用器。 多路复用器电路包括多路复用器（例如，由PLD中的多条互连线驱动），由多路复用器驱动的逻辑门（例如，反相器）和性能补偿电路。 性能补偿电路耦合到逆变器的输出端子，并具有补偿使能输入端子。 性能补偿电路被耦合以基于在补偿使能输入端上提供的信号的值来调整逻辑门的跳变点。

公开(公告)号：US07362129B1

公开(公告)日：2008-04-22

申请号：US11449198

申请日：2006-06-08

申请人： Arifur Rahman

发明人： Arifur Rahman

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H03K17/005 ,  H03K17/302 ,  H03K17/6872 ,  H03K19/00384 ,  H03K19/1737 ,  H03K2005/00123 ,  H03K2005/00136

摘要： Methods of compensating for process variations in an integrated circuit. Multiplexer circuits can be programmed to balance the rising and falling delays through the circuits in the presence of process variations. These multiplexer circuits can be used, for example, as programmable interconnect multiplexers in the interconnect structures of PLDs. During wafer sort or final test, a process corner can be determined for each die. One or more E-fuses can be set to predetermined level(s) to program the process corner information into the die, or the values can be stored in some other type of non-volatile memory. The stored values are utilized by the programmable multiplexer circuits to optionally adjust the rising and/or falling delays through the multiplexer circuits to achieve a balance between the rising and falling delays.

摘要翻译： 补偿集成电路中工艺变化的方法。 可以对多路复用器电路进行编程，以在存在过程变化的情况下平衡通过电路的上升和下降延迟。 这些多路复用器电路可以例如用作PLD的互连结构中的可编程互连多路复用器。 在晶片分选或最终测试期间，可以确定每个模具的工艺角。 可以将一个或多个电子熔丝设置到预定级别以将过程角信息编程到管芯中，或者可以将值存储在某种其他类型的非易失性存储器中。 所存储的值被可编程多路复用器电路用于可选地调整通过多路复用器电路的上升和/或下降延迟以实现上升和下降延迟之间的平衡。

公开(公告)号：US06967500B1

公开(公告)日：2005-11-22

申请号：US10397669

申请日：2003-03-26

申请人： Mou C. Lin ,  William Andrews ,  Arifur Rahman

发明人： Mou C. Lin ,  William Andrews ,  Arifur Rahman

IPC分类号： H03K17/16 ,  H04L25/02

CPC分类号： H04L25/0278 ,  H03K17/164

摘要： An electronic circuit with programmable terminations includes a circuit block, signal pads coupled to the circuit block, programmable termination circuits each associated with a corresponding one of the signal pads, and a reference circuit operative to generate one or more control signals for application to the programmable termination circuits. A given one of the programmable termination circuits is configurable independently of at least one of the other programmable termination circuits into one of a plurality of termination states. Preferably, the programmable termination circuits are each independently configurable to provide a particular termination resistance and a particular supply terminal connection type for the associated signal pad. The invention is particularly well suited for use in integrated circuit applications, such as, for example, those involving FPGAs, FPSCs and ASICs.

摘要翻译： 具有可编程端接的电子电路包括电路块，耦合到电路块的信号焊盘，每个与相应的一个信号焊盘相关联的可编程终端电路，以及可用于产生一个或多个控制信号以用于可编程 终端电路。 可编程终端电路中的给定一个可独立于至少一个其他可编程终端电路配置成多个终止状态之一。 优选地，可编程终端电路各自独立地可配置以提供特定的终端电阻和用于相关联的信号焊盘的特定供电端子连接类型。 本发明特别适用于集成电路应用，例如涉及FPGA，FPSC和ASIC的那些应用。

公开(公告)号：US06943583B1

公开(公告)日：2005-09-13

申请号：US10671378

申请日：2003-09-25

申请人： William B. Andrews ,  Mou C. Lin ,  Harold Scholz ,  Arifur Rahman

发明人： William B. Andrews ,  Mou C. Lin ,  Harold Scholz ,  Arifur Rahman

IPC分类号： H03K19/177

CPC分类号： H03K19/17744

摘要： A programmable device such as a field-programmable gate array (FPGA) has programmable I/O circuitry. In one embodiment, a programmable I/O circuit (PIC) associated with at least first and second pads of the device has an output buffer that is selectively connected to the first and second pads via corresponding first and second transmission gates. The transmission gates enable an outgoing signal from the output buffer to be individually and selectively presented at the pads, while reducing the capacitive loading at each pad when the corresponding transmission gate is open (i.e., when the outgoing signal is not to be presented at that pad).

摘要翻译： 诸如现场可编程门阵列（FPGA）的可编程器件具有可编程I / O电路。 在一个实施例中，与设备的至少第一和第二焊盘相关联的可编程I / O电路（PIC）具有经由对应的第一和第二传输门选择性地连接到第一和第二焊盘的输出缓冲器。 传输门允许来自输出缓冲器的输出信号被单独地选择地呈现在焊盘处，同时当相应的传输门打开时减小每个焊盘处的容性负载（即，当不输出信号时， 垫）。