公开(公告)号：US06721046B1

公开(公告)日：2004-04-13

申请号：US09903885

申请日：2001-07-12

申请人： Arvind Halliyal ,  Bhanwar Singh ,  Ramkumar Subramanian

发明人： Arvind Halliyal ,  Bhanwar Singh ,  Ramkumar Subramanian

IPC分类号： G01B1100

CPC分类号： H01L21/28185 ,  G01N21/4788 ,  G01N21/55 ,  G01N21/8422 ,  G01N2021/4126 ,  G01N2021/4735 ,  G01N2021/8416 ,  H01L21/28202 ,  H01L22/26 ,  H01L29/518

摘要： A system for regulating nitrided gate oxide layer formation is provided. The system includes one or more light sources, each light source directing light to one or more nitrided gate oxide layers being deposited and/or formed on a wafer. Light reflected from the nitrided gate oxide layers is collected by a measuring system, which processes the collected light. The collected light is indicative of the nitrogen concentration of the respective nitrided gate oxide layers on the wafer. The measuring system provides nitrogen concentration related data to a processor that determines the nitrogen concentration of the respective nitrided gate oxide layers on the wafer. The system also includes one or more nitrided gate oxide layer formers where a nitride gate oxide former corresponds to a respective portion of the wafer and provides for nitrided gate oxide layer formation thereon. The processor selectively controls the nitrided gate oxide layer formers to regulate nitrided gate oxide layer formation on the respective nitrided gate oxide layer formations on the wafer, and particularly to control, in situ, the amount of nitrogen incorporated into the gate oxide layer.

摘要翻译： 提供了一种用于调节氮化栅氧化层形成的系统。 该系统包括一个或多个光源，每个光源将光引导到在晶片上沉积和/或形成的一个或多个氮化栅极氧化物层。 从氮化栅氧化层反射的光被测量系统收集，该系统处理所收集的光。 所收集的光表示晶片上相应的氮化栅极氧化物层的氮浓度。 测量系统向处理器提供氮浓度相关数据，该处理器确定晶片上相应的氮化栅极氧化物层的氮浓度。 该系统还包括一个或多个氮化栅极氧化物层形成器，其中氮化物栅极氧化物形成体对应于晶片的相应部分并且在其上形成氮化的栅极氧化物层。 处理器选择性地控制氮化栅极氧化物层形成器来调节晶片上相应的氮化栅极氧化物层形成物上的氮化栅极氧化物层形成，并且特别地原位控制掺入到栅极氧化物层中的氮的量。

公开(公告)号：US06641963B1

公开(公告)日：2003-11-04

申请号：US09845239

申请日：2001-04-30

申请人： Bharath Rangarajan ,  Michael K. Templeton ,  Bhanwar Singh ,  Ramkumar Subramanian

发明人： Bharath Rangarajan ,  Michael K. Templeton ,  Bhanwar Singh ,  Ramkumar Subramanian

IPC分类号： G03F900

CPC分类号： G03F7/38 ,  G03B27/52

摘要： A system for regulating temperature of a post exposure baking process is provided. The system includes one or more light sources, each light source directing light to one or more gratings being baked and hardened on a wafer. Light reflected from the gratings is collected by a measuring system, which processes the collected light. Light passing through the gratings may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the baking and hardening of the respective portions of the wafer. The measuring system provides baking and hardening related data to a processor that determines the baking and hardening of the respective portions of the wafer. The system also includes a plurality of temperature controlling devices, each such device corresponds to a respective portion of the wafer and provides for the heating and/or cooling thereof. The processor selectively controls the temperature controlling devices so as to regulate temperature of the respective portions of the wafer.

摘要翻译： 提供了一种用于调节后曝光烘烤处理温度的系统。 该系统包括一个或多个光源，每个光源将光引导到在晶片上被烘烤和硬化的一个或多个光栅。 从光栅反射的光被测量系统收集，该系统处理收集的光。 通过光栅的光可以类似地由处理所收集的光的测量系统收集。 所收集的光表示晶片的各个部分的烘烤和硬化。 测量系统向处理器提供烘烤和硬化相关数据，该处理器确定晶片的相应部分的烘烤和硬化。 该系统还包括多个温度控制装置，每个这样的装置对应于晶片的相应部分并提供其加热和/或冷却。 处理器选择性地控制温度控制装置，以调节晶片各部分的温度。

公开(公告)号：US06630361B1

公开(公告)日：2003-10-07

申请号：US09894701

申请日：2001-06-28

申请人： Bhanwar Singh ,  Bharath Rangarajan ,  Michael K. Templeton ,  Ramkumar Subramanian ,  Cristina Cheung

发明人： Bhanwar Singh ,  Bharath Rangarajan ,  Michael K. Templeton ,  Ramkumar Subramanian ,  Cristina Cheung

IPC分类号： H01L2100

CPC分类号： H01L22/20 ,  G01N21/47 ,  G01N21/9501 ,  G01N21/956 ,  H01L21/67253

摘要： A system for regulating a gaseous phase chemical trim process is provided. The system includes one or more light sources, each light source directing light to one or more features and/or gratings on a wafer. Light reflected from the features and/or gratings is collected by a measuring system, which processes the collected light. The collected light is indicative of the dimensions achieved at respective portions of the wafer. The measuring system provides trimming related data to a processor that determines the acceptability of the trimming of the respective portions of the wafer. The system also includes one or more trimming devices, each such device corresponding to a portion of the wafer and providing for the trimming thereof. The processor selectively controls the trimming devices to regulate trimming of the portions of the wafer.

摘要翻译： 提供了一种用于调节气相化学修饰过程的系统。 该系统包括一个或多个光源，每个光源将光引导到晶片上的一个或多个特征和/或光栅。 从特征和/或光栅反射的光由测量系统收集，该系统处理收集的光。 所收集的光指示在晶片的相应部分处获得的尺寸。 测量系统向处理器提供修剪相关数据，该处理器确定了晶片各部分的修整的可接受性。 该系统还包括一个或多个修整装置，每个这样的装置对应于晶片的一部分并提供其修剪。 处理器选择性地控制修整装置来调节对晶片的部分的修整。

公开(公告)号：US06602727B1

公开(公告)日：2003-08-05

申请号：US10133874

申请日：2002-04-26

申请人： Bharath Rangarajan ,  Bhanwar Singh ,  Ramkumar Subramanian

发明人： Bharath Rangarajan ,  Bhanwar Singh ,  Ramkumar Subramanian

IPC分类号： H01L2166

CPC分类号： H01L22/20

摘要： A system for regulating an exposure condition determining process is provided. The system includes one or more light sources, each light source directing light to one or more gratings exposed on one or more portions of a wafer. Light reflected from the gratings is collected by a measuring system, which processes the collected light. Light passing through the gratings may similarly be collected by the measuring system, which processes the collected light. The collected light is analyzed to determine whether exposure conditions should be adapted prior to exposing a pattern on the wafer. The measuring system provides grating signature data to a processor that determines the acceptability of the exposure condition by comparing determined signatures to desired signatures. The system also includes an exposing system that can be controlled to change exposure conditions. The processor selectively controls the exposing system, via the exposer driving system, to adapt such exposure conditions.

摘要翻译： 提供一种用于调节曝光条件确定过程的系统。 该系统包括一个或多个光源，每个光源将光引导到暴露在晶片的一个或多个部分上的一个或多个光栅。 从光栅反射的光被测量系统收集，该系统处理收集的光。 通过光栅的光可以类似地由处理所收集的光的测量系统收集。 分析收集的光以确定在将图案暴露在晶片之前是否应适应曝光条件。 测量系统向处理器提供光栅签名数据，该处理器通过将确定的签名与期望的签名进行比较来确定曝光条件的可接受性。 该系统还包括可被控制以改变曝光条件的曝光系统。 处理器通过曝光器驱动系统选择性地控制曝光系统，以适应这种曝光条件。

公开(公告)号：US06583871B1

公开(公告)日：2003-06-24

申请号：US09911238

申请日：2001-07-23

申请人： Bharath Rangarajan ,  Bhanwar Singh ,  Khoi A. Phan ,  Ramkumar Subramanian

发明人： Bharath Rangarajan ,  Bhanwar Singh ,  Khoi A. Phan ,  Ramkumar Subramanian

IPC分类号： G01N2100

CPC分类号： G01N21/956 ,  G01N21/9501

摘要： A system adapted to provide in-situ detection of closed area defects and a method for the same is provided. The system comprises a light source for directing light on to a wafer having a grating pattern etched thereon; a light detector for collecting the light reflected from the wafer; a processor operatively coupled to the light detector for converting the collected light into data associated with the grating pattern and determining the presence of the closed area defect; and a controller operatively coupled to the processor for determining whether the wafer requires additional processing to repair the closed area defect.

摘要翻译： 提供一种适于提供闭合区域缺陷的原位检测的系统及其方法。 该系统包括用于将光引导到具有蚀刻在其上的光栅图案的晶片的光源; 用于收集从晶片反射的光的光检测器; 处理器，其可操作地耦合到所述光检测器，用于将所收集的光转换成与所述光栅图案相关联的数据，并确定所述封闭区域缺陷的存在; 以及可操作地耦合到所述处理器的控制器，用于确定所述晶片是否需要额外的处理以修复所述封闭区域缺陷。

公开(公告)号：US06579651B2

公开(公告)日：2003-06-17

申请号：US10175923

申请日：2002-06-20

申请人： Ramkumar Subramanian ,  Khoi A. Phan ,  Bhanwar Singh ,  Bharath Rangarajan

发明人： Ramkumar Subramanian ,  Khoi A. Phan ,  Bhanwar Singh ,  Bharath Rangarajan

IPC分类号： G03F900

CPC分类号： G03F1/70 ,  G03F7/70433 ,  G03F7/70441

摘要： The present invention relates to a system and method of modifying mask layout data to improve the fidelity of mask manufacture. The system and method include determining the difference between the mask layout design and the mask features as written, and generating sizing corrections. The sizing corrections can be used to modify the mask layout data, and/or stored in a database.

公开(公告)号：US06545753B2

公开(公告)日：2003-04-08

申请号：US09893186

申请日：2001-06-27

申请人： Ramkumar Subramanian ,  Bhanwar Singh ,  Michael K. Templeton

发明人： Ramkumar Subramanian ,  Bhanwar Singh ,  Michael K. Templeton

IPC分类号： G01N2100

CPC分类号： H01L21/7681 ,  G01N21/4738 ,  H01J37/32935

摘要： A system for monitoring and/or controlling an etch process associated with a dual damascene process via scatterometry based processing is provided. The system includes one or more light sources, each light source directing light to one or more features and/or gratings on a wafer. Light reflected from the features and/or gratings is collected by a measuring system, which processes the collected light. The collected light is indicative of the etch results achieved at respective portions of the wafer. The measuring system provides etching related data to a processor that determines the desirability of the etching of the respective portions of the wafer. The system also includes one or more etching devices, each such device corresponding to a portion of the wafer and providing for the etching thereof. The processor produces a real time feed forward information to control the etch process, in particular, terminating the etch process when desired end points have been encountered.

摘要翻译： 提供了一种用于通过基于散射测量的处理来监测和/或控制与双镶嵌工艺相关联的蚀刻工艺的系统。 该系统包括一个或多个光源，每个光源将光引导到晶片上的一个或多个特征和/或光栅。 从特征和/或光栅反射的光由测量系统收集，该系统处理收集的光。 所收集的光指示在晶片的各个部分实现的蚀刻结果。 测量系统向处理器提供蚀刻相关数据，该处理器确定晶片的相应部分的蚀刻的可取性。 该系统还包括一个或多个蚀刻装置，每个这样的装置对应于晶片的一部分并提供其蚀刻。 处理器产生实时前馈信息以控制蚀刻工艺，特别是在遇到所需端点时终止蚀刻工艺。

公开(公告)号：US06486078B1

公开(公告)日：2002-11-26

申请号：US09643531

申请日：2000-08-22

申请人： Bharath Rangarajan ,  Ramkumar Subramanian ,  Bhanwar Singh

发明人： Bharath Rangarajan ,  Ramkumar Subramanian ,  Bhanwar Singh

IPC分类号： H01L2131

CPC分类号： H01L21/0212 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/02343 ,  H01L21/31695

摘要： One aspect of the present invention relates to a method of forming a low k material layer on a semiconductor substrate, involving the steps of depositing a mixture containing a low k material and a casting solvent on the semiconductor substrate; optionally contacting the mixture with a transition solvent whereby the casting solvent is removed from the mixture to form a second mixture containing the low k material and the transition solvent; contacting the second mixture with a supercritical fluid whereby the transition solvent is removed from the second mixture; and permitting the supercritical fluid to evaporate thereby forming the low k material layer.

摘要翻译： 本发明的一个方面涉及在半导体衬底上形成低k材料层的方法，包括在半导体衬底上沉积含有低k材料和浇铸溶剂的混合物的步骤; 任选地将混合物与过渡溶剂接触，由此从混合物中除去浇注溶剂以形成含有低k材料和过渡溶剂的第二混合物; 使所述第二混合物与超临界流体接触，由此从所述第二混合物中除去所述过渡溶剂; 并允许超临界流体蒸发，从而形成低k材料层。

公开(公告)号：US06459482B1

公开(公告)日：2002-10-01

申请号：US09729294

申请日：2000-12-04

申请人： Bhanwar Singh ,  Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Michael K. Templeton ,  Sanjay K. Yedur ,  Bryan K. Choo

发明人： Bhanwar Singh ,  Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Michael K. Templeton ,  Sanjay K. Yedur ,  Bryan K. Choo

IPC分类号： G01J110

CPC分类号： H01J37/28 ,  H01J2237/2826

摘要： The present invention provides SEM systems, SEM calibration standards, and SEM calibration methods that improved accuracy in critical dimension measurements. The calibration standards have features formed with an amorphous material such as amorphous silicon. Amorphous materials lack the crystal grain structure of materials such as polysilicon and are capable of providing sharper edged features and higher accuracy patterns than grained materials. The amorphous material can be bound to a silicon wafer substrate through an intermediate layer of material, such as silicon dioxide. Where the intermediate layer is insulating material, as is silicon dioxide, the intermediate layer may be patterned with gaps to provide for electrical communication between the amorphous silicon and the silicon wafer. Charges imparted to the amorphous silicon during electron beam scanning may thereby drain to the silicon wafer rather than accumulating to a level where they would distort the electron beam.

摘要翻译： 本发明提供SEM系统，SEM校准标准和SEM校准方法，提高了临界尺寸测量的精度。 校准标准品具有非晶体材料如非晶硅形成的特征。 无定形材料缺乏诸如多晶硅的材料的晶粒结构，并且能够提供比颗粒材料更尖锐的边缘特征和更高精度的图案。 非晶材料可以通过诸如二氧化硅的材料的中间层与硅晶片衬底结合。 在中间层是绝缘材料的情况下，如二氧化硅那样，中间层可以用间隙图案化以提供非晶硅和硅晶片之间的电连通。 因此，在电子束扫描期间赋予非晶硅的电荷可以从而被排出到硅晶片，而不是积聚到它们会使电子束变形的水平。

公开(公告)号：US06451621B1

公开(公告)日：2002-09-17

申请号：US10050732

申请日：2002-01-16

申请人： Bharath Rangarajan ,  Bhanwar Singh ,  Ramkumar Subramanian

发明人： Bharath Rangarajan ,  Bhanwar Singh ,  Ramkumar Subramanian

IPC分类号： H01L2166

CPC分类号： H01L22/12

摘要： The present invention provides systems and methods wherein scatterometry is used to control an implant processes, such as an angled implant process. According to the invention, data relating to resist dimensions is obtained by scatterometry prior to an the implant process. The data is used to determine whether a resist is suitable for an implant process and/or determine an appropriate condition, such as an angle of implant or implantation dose, for an implant process.

摘要翻译： 本发明提供了系统和方法，其中使用散射法来控制植入过程，例如成角度的植入过程。 根据本发明，与抗蚀剂尺寸相关的数据通过在植入工艺之前的散射测量获得。 该数据用于确定抗蚀剂是否适合于植入过程，和/或确定用于植入过程的适当条件，例如植入角度或植入剂量。