公开(公告)号：US20070037098A1

公开(公告)日：2007-02-15

申请号：US11161624

申请日：2005-08-10

申请人： Brent Anderson ,  Jed Rankin

发明人： Brent Anderson ,  Jed Rankin

IPC分类号： G03F7/20

CPC分类号： G03F7/70466 ,  G03F1/36 ,  G03F1/70 ,  G03F7/70433

摘要： Systems and methods for modifying features of a semiconductor device. The systems and methods of the invention modify features of a semiconductor device according to the amount of exposure dose of light to which a common reticle field of a semiconductor device is exposed. A mask, or a thin film provided on a mask, having sub-resolutions provided thereon determines the amount of exposure dose to which various parts of the reticle field is exposed during the exposure. As a result, different features within the same reticle field can exhibit different dimensions even though exposed to the same exposure dose.

摘要翻译： 用于修改半导体器件特征的系统和方法。 本发明的系统和方法根据半导体器件的公共掩模版场所暴露的光的曝光量的量来修改半导体器件的特征。 提供在掩模上的掩模或薄膜具有其上提供的子分辨率，确定在曝光期间掩模版场的各个部分暴露于哪一个曝光剂量。 结果，即使暴露于相同的曝光剂量，相同掩模版领域内的不同特征也可呈现不同的尺寸。

公开(公告)号：US20070010049A1

公开(公告)日：2007-01-11

申请号：US11160360

申请日：2005-06-21

申请人： Brent Anderson ,  Edward Nowak ,  Jed Rankin ,  William Clark

发明人： Brent Anderson ,  Edward Nowak ,  Jed Rankin ,  William Clark

IPC分类号： H01L21/8234

CPC分类号： H01L29/78606 ,  H01L27/0248 ,  H01L29/42384 ,  H01L29/785

摘要： A fin-type field effect transistor has an insulator layer above a substrate and a fin extending above the insulator layer. The fin has a channel region, and source and drain regions. A gate conductor is positioned over the channel region. The insulator layer includes a heat dissipating structural feature adjacent the fin, and a portion of the gate conductor contacts the heat dissipating structural feature. The heat dissipating structural feature can comprise a recess within the insulator layer or a thermal conductor extending through the insulator layer.

公开(公告)号：US20060292772A1

公开(公告)日：2006-12-28

申请号：US11160457

申请日：2005-06-24

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L21/8234 ,  H01L21/336 ,  H01L21/84

CPC分类号： H01L21/823437 ,  H01L21/823412 ,  H01L21/84 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/78609 ,  Y10S257/903

摘要： Disclosed is a method of forming a pair of transistors by epitaxially growing a pair of silicon fins on a silicon germanium fin on a bulk wafer. In one embodiment a gate conductor between the fins is isolated from a conductor layer on the bulk wafer so a front gate may be formed. In another embodiment a gate conductor between the fins contacts a conductor layer on the bulk wafer so a back gate may be formed. In yet another embodiment both of the previous structures are simultaneously formed on the same bulk wafer. The method allow the pairs of transistors to be formed with a variety of features (e.g., strained fins, a space between two fins that is approximately 0.5 to 3 times greater than a width of a single fin, a first dielectric layer on the inner sidewalls of each pair of fins with a different thickness and/or a different dielectric material than a second dielectric layer on the outer sidewalls of each pair of fins, etc.).

摘要翻译： 公开了通过在体晶片上的硅锗翅片上外延生长一对硅散热片来形成一对晶体管的方法。 在一个实施例中，翅片之间的栅极导体与体晶片上的导体层隔离，因此可以形成前栅极。 在另一个实施例中，翅片之间的栅极导体接触体晶片上的导体层，因此可形成背栅。 在另一个实施例中，两个先前的结构同时形成在相同的体晶片上。 该方法允许成对的晶体管形成有各种特征（例如，应变翅片，两个翅片之间的空间，比单个鳍片的宽度大约0.5至3倍，内侧壁上的第一介电层 每个翅片具有与每对翅片的外侧壁上的第二介电层不同的厚度和/或不同的电介质材料等）。

公开(公告)号：US20060286724A1

公开(公告)日：2006-12-21

申请号：US11160361

申请日：2005-06-21

申请人： Brent Anderson ,  Matthew Breitwisch ,  Edward Nowak

发明人： Brent Anderson ,  Matthew Breitwisch ,  Edward Nowak

IPC分类号： H01L21/84 ,  H01L29/76

CPC分类号： H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

摘要： Disclosed is a tri-gate field effect transistor with a back gate and the associated methods of forming the transistor. Specifically, a back gate is incorporated into a lower portion of a fin. A tri-gate structure is formed on the fin and is electrically isolated from the back gate. The back gate can be used to control the threshold voltage of the FET. In one embodiment the back gate extends to an n-well in a p-type silicon substrate. A contact to the n-well allows electrical voltage to be applied to the back gate. A diode created between the n-well and p-substrate isolates the current flowing through the n-well from other devices on the substrate so that the back gate can be independently biased. In another embodiment the back gate extends to n-type polysilicon layer on an insulator layer on a p-type silicon substrate. A contact to the n-type polysilicon layer allows electrical voltage to be applied to the back gate. A trench isolation structure extending through the polysilicon layer to the insulator layer isolates current flowing through the polysilicon layer from other devices on the silicon substrate.

摘要翻译： 公开了具有背栅的三栅场效应晶体管和形成晶体管的相关方法。 具体地说，后门结合在翅片的下部。 三栅结构形成在翅片上并与后门电隔离。 背栅可用于控制FET的阈值电压。 在一个实施例中，背栅极延伸到p型硅衬底中的n阱。 与n阱的接触允许将电压施加到后门。 在n阱和p衬底之间产生的二极管将流过n阱的电流与衬底上的其他器件隔离，使得后栅极可以被独立地偏置。 在另一个实施例中，背栅极延伸到p型硅衬底上的绝缘体层上的n型多晶硅层。 与n型多晶硅层的接触允许电压施加到后门。 通过多晶硅层延伸到绝缘体层的沟槽隔离结构将流过多晶硅层的电流与硅衬底上的其它器件隔离。

公开(公告)号：US20060228862A1

公开(公告)日：2006-10-12

申请号：US10907568

申请日：2005-04-06

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L21/00

CPC分类号： H01L21/823425 ,  H01L21/823475 ,  H01L27/0207 ,  H01L29/78 ,  H01L29/7851 ,  H01L2029/7858

摘要： A complementary metal oxide semiconductor field effect transistor (CMOS FET) design layout and method of fabrication are disclosed that provide a long gate and dense pitch in which gate contacts are positioned directly on top of the gates, and source and drain contacts are made into contact CA bars with contact pads outside the RX (active silicon conductor) region of the FET.

摘要翻译： 公开了互补金属氧化物半导体场效应晶体管（CMOS FET）的制造布局和制造方法，其提供了长栅极和密集间距，其中栅极触点直接位于栅极的顶部，并且源极和漏极触点被形成接触 CA焊条在FET的RX（有源硅导体）区域外部具有接触焊盘。

公开(公告)号：US20060183289A1

公开(公告)日：2006-08-17

申请号：US11401786

申请日：2006-04-11

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L21/336

CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L27/11 ,  H01L29/66795 ,  H01L29/785 ,  Y10S257/903

摘要： A compact semiconductor structure having back gate(s) for controlling threshold voltages and associated method of formation is disclosed. Fabrication of the semiconductor structure starts with a semiconductor region formed directly on an underlying electrically isolating layer. Then, a mandrel and a spacer are formed on the semiconductor region. Next, a back gate region is formed separated from the semiconductor region by a back gate isolating layer and covered by an inter-gate isolating layer. Next, a portion of the semiconductor region beneath the mandrel is removed so as to form an active region adjacent to the removed portion of the semiconductor region. Finally, a main gate region is formed in place of the removed portion of the semiconductor region and on the inter-gate isolating layer. The main gate region is separated from the active region by a main gate isolating layer and separated from the back gate region by the inter-gate isolating layer.

公开(公告)号：US20060163673A1

公开(公告)日：2006-07-27

申请号：US11340354

申请日：2006-01-26

申请人： Brent Anderson ,  Edward Nowak

发明人： Brent Anderson ,  Edward Nowak

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L21/823807 ,  H01L21/823828 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/66553 ,  H01L29/66795

摘要： A field effect transistor (FET) comprising an isolation layer, a source region positioned over the isolation layer, a drain region positioned over the isolation layer, a bifurcated silicide gate region positioned over the channel region, and a gate oxide layer adjacent to the gate region, wherein the gate oxide layer comprises an alkali metal ion implanted at a dosage calculated based on threshold voltage test data provided by a post silicide electrical test conducted on said FET, wherein the alkali metal ion comprises any of cesium and rubidium.

摘要翻译： 包括隔离层的场效应晶体管（FET），位于隔离层上方的源极区域，位于隔离层上方的漏极区域，位于沟道区域上方的分叉硅化物栅极区域以及邻近栅极的栅氧化层 区，其中所述栅极氧化物层包含以基于通过在所述FET上进行的后硅化物电测试提供的阈值电压测试数据计算的剂量注入的碱金属离子，其中所述碱金属离子包含任何铯和铷。

公开(公告)号：US20060124982A1

公开(公告)日：2006-06-15

申请号：US10905094

申请日：2004-12-15

申请人： Herbert Ho ,  John Barth ,  Ramachandra Divakaruni ,  Wayne Ellis ,  Johnathan Faltermeier ,  Brent Anderson ,  Subramanian Iyer ,  Deok-Kee Kim ,  Randy Mann ,  Paul Parries

发明人： Herbert Ho ,  John Barth ,  Ramachandra Divakaruni ,  Wayne Ellis ,  Johnathan Faltermeier ,  Brent Anderson ,  Subramanian Iyer ,  Deok-Kee Kim ,  Randy Mann ,  Paul Parries

IPC分类号： H01L29/94 ,  H01L27/108

CPC分类号： H01L27/0805 ,  H01L29/66181 ,  H01L29/945

摘要： A novel trench-type decoupling capacitor structure and low-cost manufacturing process to create trench decoupling capacitors (decaps). In a unique aspect, the invention necessitates the addition of only a simplified trench to a base logic design.

摘要翻译： 一种新颖的沟槽型去耦电容器结构和低成本制造工艺，以创建沟槽去耦电容器（decaps）。 在一个独特的方面，本发明仅需要在基本逻辑设计中添加简化的沟槽。

公开(公告)号：US20060084212A1

公开(公告)日：2006-04-20

申请号：US11200271

申请日：2005-08-09

申请人： Brent Anderson ,  Edward Nowak ,  Jed Rankin

发明人： Brent Anderson ,  Edward Nowak ,  Jed Rankin

IPC分类号： H01L21/8234

CPC分类号： H01L29/785 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

摘要： A planar substrate device integrated with fin field effect transistors (FinFETs) and a method of manufacture comprises a silicon-on-insulator (SOI) wafer comprising a substrate; a buried insulator layer over the substrate; and a semiconductor layer over the buried insulator layer. The structure further comprises a FinFET over the buried insulator layer and a field effect transistor (FET) integrated in the substrate, wherein the FET gate is planar to the FinFET gate. The structure further comprises retrograde well regions configured in the substrate. In one embodiment, the structure further comprises a shallow trench isolation region configured in the substrate.

摘要翻译： 与鳍状场效应晶体管（FinFET）集成的平面基板器件和制造方法包括：包括衬底的绝缘体上硅（SOI）晶片; 衬底上的掩埋绝缘体层; 以及掩埋绝缘体层上的半导体层。 所述结构还包括在所述掩埋绝缘体层上的FinFET和集成在所述衬底中的场效应晶体管（FET），其中所述FET栅极与所述FinFET栅极平面。 该结构还包括在衬底中配置的逆行阱区。 在一个实施例中，该结构还包括在衬底中配置的浅沟槽隔离区域。

公开(公告)号：US20060060935A1

公开(公告)日：2006-03-23

申请号：US10711425

申请日：2004-09-17

申请人： Brent Anderson ,  John Ellis-Monaghan

发明人： Brent Anderson ,  John Ellis-Monaghan

IPC分类号： H01L29/76

CPC分类号： H01L21/76224

摘要： A novel isolation structure in semiconductor integrated circuits (IC) and the fabrication method of the same. The isolation structure comprises (a) semiconductor a substrate, and (b) an electric isolation region embedded in and at top of the semiconductor substrate, wherein the electric isolation region comprises (i) a bubble-implanted semiconductor region and (ii) an electrically insulating cap region on top of the bubble-implanted semiconductor region.

摘要翻译： 半导体集成电路（IC）中的新型隔离结构及其制造方法。 隔离结构包括（a）衬底半导体，和（b）嵌入在半导体衬底中和顶部的电隔离区，其中电隔离区包括（i）注入气泡的半导体区和（ii）电 在气泡注入半导体区域顶部的绝缘帽区域。