公开(公告)号：US06326662B1

公开(公告)日：2001-12-04

申请号：US09633643

申请日：2000-08-07

申请人： Chia-Ta Hsieh ,  Chrong Jung Lin ,  Shui-Hung Chen ,  Di-Son Kuo

发明人： Chia-Ta Hsieh ,  Chrong Jung Lin ,  Shui-Hung Chen ,  Di-Son Kuo

IPC分类号： H01L29788

CPC分类号： H01L27/11519 ,  H01L27/115 ,  H01L27/11521

摘要： A method of forming split gate electrode MOSFET devices comprises the following steps. Form a tunnel oxide layer over a semiconductor substrate. Form a floating gate electrode layer over the tunnel oxide layer. Form a masking cap over the floating gate electrode layer. Pattern gate electrode stacks formed by the tunnel oxide layer and the floating gate electrode layer in the pattern of the masking cap. Pattern source line slots in the center of the gate electrode stacks down to the substrate. Form source regions at the base of the source lines slots. Form intermetal dielectric and control gate layers over the substrate covering the stacks. Pattern the intermetal dielectric and control gate layers into adjacent mirror image split gate electrode pairs. Form self-aligned drain regions.

摘要翻译： 形成分离栅电极MOSFET器件的方法包括以下步骤。 在半导体衬底上形成隧道氧化层。 在隧道氧化物层上形成浮栅电极层。 在浮栅电极层上形成掩蔽帽。 掩模盖的图案中的隧道氧化物层和浮栅电极层形成的栅极电极堆叠。 栅电极中心的图案源极线槽向下堆叠到衬底。 在源线插槽的底部形成源区。 在覆盖堆叠的衬底上形成金属间电介质和控制栅极层。 将金属间电介质和控制栅极层图案化成相邻的镜像分离栅电极对。 形成自对准漏极区。

公开(公告)号：US20060046403A1

公开(公告)日：2006-03-02

申请号：US10931547

申请日：2004-08-31

申请人： Wen-Ting Chu ,  Chia-Ta Hsieh ,  Hung-Cheng Sung

发明人： Wen-Ting Chu ,  Chia-Ta Hsieh ,  Hung-Cheng Sung

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/3205

CPC分类号： H01L29/512 ,  H01L21/28202 ,  H01L29/40117 ,  H01L29/518 ,  H01L29/66833

摘要： A method of forming a semiconductor device comprises forming a gate dielectric layer and a gate electrode over the gate dielectric layer on a semiconductor substrate, partially removing the gate dielectric layer to form two recesses separated by the gate dielectric layer and disposed substantially under the gate electrode, and substantially filling the two recesses with an oxide layer and a material layer to form two separated regions operable to each hold an electrical charge.

摘要翻译： 一种形成半导体器件的方法包括在半导体衬底上的栅介电层上形成栅极电介质层和栅电极，部分地去除栅极电介质层以形成由栅极电介质层分开并设置在栅电极下方的两个凹槽 并且用氧化物层和材料层基本上填充两个凹部以形成可操作以保持电荷的两个分离的区域。

公开(公告)号：US20050156224A1

公开(公告)日：2005-07-21

申请号：US11059987

申请日：2005-02-17

申请人： Chia-Ta Hsieh ,  Yi-Jiun Lin ,  Feng-Jia Shiu ,  Hung-Cheng Sung ,  Chi-Hsin Lo

发明人： Chia-Ta Hsieh ,  Yi-Jiun Lin ,  Feng-Jia Shiu ,  Hung-Cheng Sung ,  Chi-Hsin Lo

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A new method to form MOS gates in an integrated circuit device is achieved. The method is particularly useful for forming floating gates in split gate flash transistors. The method comprises providing a substrate. A dielectric layer is formed overlying the substrate. A conductor layer is formed overlying the dielectric layer. A first masking layer is deposited overlying the conductor layer. The first masking layer is patterned to selectively expose the conductor layer. A second masking layer is deposited overlying the first masking layer and the conductor layer. The second masking layer is etched back to form spacers on sidewalls of the first masking layer. The conductor layer is etched through where exposed by the first masking layer and the spacers to thereby form MOS gates in the manufacture of the integrated circuit device.

公开(公告)号：US06881629B2

公开(公告)日：2005-04-19

申请号：US10655662

申请日：2003-09-05

申请人： Chia-Ta Hsieh ,  Yi-Jiun Lin ,  Feng-Jia Shiu ,  Hung-Cheng Sung ,  Chi-Hsin Lo

发明人： Chia-Ta Hsieh ,  Yi-Jiun Lin ,  Feng-Jia Shiu ,  Hung-Cheng Sung ,  Chi-Hsin Lo

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01I21/8247

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A new method to form MOS gates in an integrated circuit device is achieved. The method is particularly useful for forming floating gates in split gate flash transistors. The method comprises providing a substrate. A dielectric layer is formed overlying the substrate. A conductor layer is formed overlying the dielectric layer. A first masking layer is deposited overlying the conductor layer. The first masking layer is patterned to selectively expose the conductor layer. A second masking layer is deposited overlying the first masking layer and the conductor layer. The second masking layer is etched back to form spacers on sidewalls of the first masking layer. The conductor layer is etched through where exposed by the first masking layer and the spacers to thereby form MOS gates in the manufacture of the integrated circuit device.

摘要翻译： 实现了在集成电路器件中形成MOS栅极的新方法。 该方法对于在分离栅极闪存晶体管中形成浮置栅极特别有用。 该方法包括提供基底。 在衬底上形成介电层。 形成覆盖在电介质层上的导体层。 第一掩模层沉积在导体层上。 图案化第一掩模层以选择性地暴露导体层。 第二掩模层沉积在第一掩模层和导体层上。 第二掩模层被回蚀刻以在第一掩模层的侧壁上形成间隔物。 通过第一掩模层和间隔物露出的导体层被蚀刻，从而在集成电路器件的制造中形成MOS栅极。

公开(公告)号：US20050054162A1

公开(公告)日：2005-03-10

申请号：US10655662

申请日：2003-09-05

申请人： Chia-Ta Hsieh ,  Yi-Jiun Lin ,  Feng-Jia Shiu ,  Hung-Cheng Sung ,  Chi-Hsin Lo

发明人： Chia-Ta Hsieh ,  Yi-Jiun Lin ,  Feng-Jia Shiu ,  Hung-Cheng Sung ,  Chi-Hsin Lo

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A new method to form MOS gates in an integrated circuit device is achieved. The method is particularly useful for forming floating gates in split gate flash transistors. The method comprises providing a substrate. A dielectric layer is formed overlying the substrate. A conductor layer is formed overlying the dielectric layer. A first masking layer is deposited overlying the conductor layer. The first masking layer is patterned to selectively expose the conductor layer. A second masking layer is deposited overlying the first masking layer and the conductor layer. The second masking layer is etched back to form spacers on sidewalls of the first masking layer. The conductor layer is etched through where exposed by the first masking layer and the spacers to thereby form MOS gates in the manufacture of the integrated circuit device.

摘要翻译： 实现了在集成电路器件中形成MOS栅极的新方法。 该方法对于在分离栅极闪存晶体管中形成浮置栅极特别有用。 该方法包括提供基底。 在衬底上形成介电层。 形成覆盖在电介质层上的导体层。 第一掩模层沉积在导体层上。 图案化第一掩模层以选择性地暴露导体层。 第二掩模层沉积在第一掩模层和导体层上。 第二掩模层被回蚀刻以在第一掩模层的侧壁上形成间隔物。 通过第一掩模层和间隔物露出的导体层被蚀刻，从而在集成电路器件的制造中形成MOS栅极。

公开(公告)号：US06569736B1

公开(公告)日：2003-05-27

申请号：US10076668

申请日：2002-02-14

申请人： Cheng-Yuan Hsu ,  Hung-Cheng Sung ,  Su-Chang Chen ,  Han-Ping Chen ,  Chia-Ta Hsieh ,  Der-Shin Shyu

发明人： Cheng-Yuan Hsu ,  Hung-Cheng Sung ,  Su-Chang Chen ,  Han-Ping Chen ,  Chia-Ta Hsieh ,  Der-Shin Shyu

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/6656 ,  H01L29/66825

摘要： A method for forming square polysilicon spacers on a split gate flash memory device by a multi-step polysilicon etch process is described. The method can be carried out by depositing a polysilicon layer on the flash memory device structure and then depositing a sacrificial layer, such as silicon oxide, on top of the polysilicon layer. The sacrificial layer has a slower etch rate than the polysilicon layer during a main etch step. The sacrificial layer overlies the flash memory device is then removed, while the sacrificial layer on the sidewall is kept intact. The polysilicon layer that overlies the flash memory device is then etched away followed by a step of removing all residual sacrificial layers. The exposed polysilicon layer is then etched to define the square polysilicon spacers on the split gate flash memory device.

摘要翻译： 描述了通过多步多晶硅蚀刻工艺在分裂栅极闪存器件上形成方形多晶硅间隔物的方法。 该方法可以通过在闪存器件结构上沉积多晶硅层，然后在多晶硅层的顶部上沉积牺牲层，例如氧化硅来进行。 在主蚀刻步骤期间，牺牲层具有比多晶硅层更慢的蚀刻速率。 覆盖闪存器件的牺牲层然后被去除，同时侧壁上的牺牲层保持完整。 然后将覆盖在闪速存储器件上的多晶硅层蚀刻掉，随后除去所有残余牺牲层的步骤。 然后蚀刻暴露的多晶硅层以在分裂栅极闪存器件上限定方形多晶硅间隔物。

公开(公告)号：US20060163686A1

公开(公告)日：2006-07-27

申请号：US11044813

申请日：2005-01-26

申请人： Shih-Chang Liu ,  Wen-Ting Chu ,  Chien-Ming Ku ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Chia-Ta Hsieh

发明人： Shih-Chang Liu ,  Wen-Ting Chu ,  Chien-Ming Ku ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Chia-Ta Hsieh

IPC分类号： H01L21/76 ,  H01L29/00

CPC分类号： H01L27/11521 ,  H01L21/76224 ,  H01L27/10894 ,  H01L27/11

摘要： A method is provided for fabrication of a semiconductor substrate having regions isolated from each other by shallow trench isolation (STI) structures protruding above a surface of the substrate by a step height. The method includes the steps of forming a bottom antireflective coating (BARC) layer overlying the surface of a semiconductor substrate and the surface of STI structures; etching back a portion of the BARC layer overlying at least one of the STI structures, and partially etching back the at least one of the STI structures, to reduce the step height by which the STI structure protrudes above the surface of the substrate; and removing a remaining portion of the BARC layer between adjacent STI structures. The method may be used to fabricate semiconductor devices including memory cells that have improved reliability.

摘要翻译： 提供了一种用于制造半导体衬底的方法，该半导体衬底具有通过在衬底的表面上突出台阶高度的浅沟槽隔离（STI）结构彼此隔离的区域。 该方法包括以下步骤：形成覆盖在半导体衬底的表面上的底部抗反射涂层（BARC）层和STI结构的表面; 蚀刻覆盖所述STI结构中的至少一个的所述BARC层的一部分，并且部分地蚀刻所述STI结构中的所述至少一个，以降低所述STI结构在所述衬底的表面上方突出的台阶高度; 以及去除相邻STI结构之间的BARC层的剩余部分。 该方法可用于制造包括具有改进的可靠性的存储器单元的半导体器件。

公开(公告)号：US07078349B2

公开(公告)日：2006-07-18

申请号：US10631842

申请日：2003-07-31

申请人： Chia-Ta Hsieh

发明人： Chia-Ta Hsieh

IPC分类号： H01L21/311

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A self-aligned conductive region to active region structure is disclosed in which parallel active regions of a semiconductor region of a substrate, which extends to a surface, are separated by STI regions. The STI regions have an insulator liner layer grown over their sides and are filled with an insulator filler layer. Equally spaced gate insulator regions, formed prior to the STI regions, are disposed over the active regions and overlap a portion of the insulator liner layer. Conductive regions, formed prior to the STI regions, are disposed over the gate insulator regions.

摘要翻译： 公开了一种自对准导电区域到有源区域结构，其中延伸到表面的衬底的半导体区域的平行有源区域被STI区域分离。 STI区域具有在其侧面生长的绝缘体衬垫层，并且填充有绝缘体填充层。 在STI区之前形成的相等间隔的栅极绝缘体区域设置在有源区上方并与绝缘衬层的一部分重叠。 在STI区之前形成的导电区域设置在栅极绝缘体区域上。

公开(公告)号：US20060046410A1

公开(公告)日：2006-03-02

申请号：US11258423

申请日：2005-10-25

申请人： Chia-Ta Hsieh

发明人： Chia-Ta Hsieh

IPC分类号： H01L21/8222 ,  H01L21/331 ,  H01L21/8238

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881

摘要： A structure is disclosed to improve the coupling ratio of top gate to floating gate in flash memory cells. Parallel active regions are surrounded by isolation regions and are disposed over a semiconductor region of a substrate. The isolation regions have a portion within and a portion above the semiconductor region. The semiconductor region under the active regions is doped in the vicinity of the surface to adjust the threshold voltage Insulator spacers are disposed against the sidewalls of the portion of the isolation regions that are above the semiconductor region and they taper so they are wider near the semiconductor region, and thus the spacing between neighboring insulator spacers on the same active region decreases closer to the semiconductor region Conductive floating gates spaced along the active regions are separated from the semiconductor region by a floating gate insulator layer, are disposed between insulator spacers and extend about to the height of the isolation regions. Top gates, comprised of conductive stripes that are perpendicular to the active regions, are disposed over floating gates from which they are separated by a top gate insulator layer.

摘要翻译： 公开了一种结构来提高闪存单元中顶栅与浮栅的耦合比。 平行的有源区域被隔离区包围，并设置在衬底的半导体区域上。 隔离区域具有在半导体区域之内和部分之上的部分。 在有源区下面的半导体区域被掺杂在表面附近以调整阈值电压绝缘体间隔物抵靠在半导体区域之上的隔离区域的部分的侧壁上，并且它们变细，使得它们在半导体附近更宽 并且因此相同有源区上的相邻绝缘体间隔物之间​​的间隔减小到靠近半导体区域。沿着有源区间隔的导电浮置栅极通过浮置栅极绝缘体层与半导体区域分离，被布置在绝缘体间隔物之间​​并且围绕 到隔离区的高度。 由垂直于有源区的导电条构成的顶栅设置在浮置栅极之上，由栅极绝缘体层分隔。

公开(公告)号：US06921695B2

公开(公告)日：2005-07-26

申请号：US10685127

申请日：2003-10-14

申请人： Hsiu Ouyang ,  Chi-Hsin Lo ,  Chen-Ming Huang ,  Chia-Ta Hsieh ,  Chia-Shiung Tsai

发明人： Hsiu Ouyang ,  Chi-Hsin Lo ,  Chen-Ming Huang ,  Chia-Ta Hsieh ,  Chia-Shiung Tsai

IPC分类号： H01L21/311 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/32138 ,  H01L21/32139 ,  H01L27/115

摘要： A split gate FET wordline electrode structure and method for forming the same including an improved polysilicon etching process including providing a semiconductor wafer process surface comprising first exposed polysilicon portions and adjacent oxide portions; forming a first oxide layer on the exposed polysilicon portions; blanket depositing a polysilicon layer on the first exposed polysilicon portions and adjacent oxide portions; forming a hardmask layer on the polysilicon layer; carrying out a multi-step reactive ion etching (RIE) process to etch through the hardmask layer and etch through a thickness portion of the polysilicon layer to form second polysilicon portions adjacent the oxide portions having upward protruding outer polysilicon fence portions; contacting the semiconductor wafer process surface with an aqueous HF solution; and, carrying out a downstream plasma etching process to remove polysilicon fence portions.