公开(公告)号：US06569736B1

公开(公告)日：2003-05-27

申请号：US10076668

申请日：2002-02-14

申请人： Cheng-Yuan Hsu ,  Hung-Cheng Sung ,  Su-Chang Chen ,  Han-Ping Chen ,  Chia-Ta Hsieh ,  Der-Shin Shyu

发明人： Cheng-Yuan Hsu ,  Hung-Cheng Sung ,  Su-Chang Chen ,  Han-Ping Chen ,  Chia-Ta Hsieh ,  Der-Shin Shyu

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/6656 ,  H01L29/66825

摘要： A method for forming square polysilicon spacers on a split gate flash memory device by a multi-step polysilicon etch process is described. The method can be carried out by depositing a polysilicon layer on the flash memory device structure and then depositing a sacrificial layer, such as silicon oxide, on top of the polysilicon layer. The sacrificial layer has a slower etch rate than the polysilicon layer during a main etch step. The sacrificial layer overlies the flash memory device is then removed, while the sacrificial layer on the sidewall is kept intact. The polysilicon layer that overlies the flash memory device is then etched away followed by a step of removing all residual sacrificial layers. The exposed polysilicon layer is then etched to define the square polysilicon spacers on the split gate flash memory device.

摘要翻译： 描述了通过多步多晶硅蚀刻工艺在分裂栅极闪存器件上形成方形多晶硅间隔物的方法。 该方法可以通过在闪存器件结构上沉积多晶硅层，然后在多晶硅层的顶部上沉积牺牲层，例如氧化硅来进行。 在主蚀刻步骤期间，牺牲层具有比多晶硅层更慢的蚀刻速率。 覆盖闪存器件的牺牲层然后被去除，同时侧壁上的牺牲层保持完整。 然后将覆盖在闪速存储器件上的多晶硅层蚀刻掉，随后除去所有残余牺牲层的步骤。 然后蚀刻暴露的多晶硅层以在分裂栅极闪存器件上限定方形多晶硅间隔物。

公开(公告)号：US06849499B2

公开(公告)日：2005-02-01

申请号：US10331370

申请日：2002-12-30

申请人： Hung-Cheng Sung ,  Han-Ping Chen ,  Cheng-Yuan Hsu

发明人： Hung-Cheng Sung ,  Han-Ping Chen ,  Cheng-Yuan Hsu

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L21/336 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method is provided for forming a flash memory cell having an amorphous silicon floating gate capped by a CVD oxide, and a control gate formed over an intergate oxide layer formed over the oxide cap. Amorphous silicon is first formed over a gate oxide layer over a substrate, followed by the forming of a silicon nitride layer over the amorphous silicon layer. Silicon nitride is patterned to have a tapered opening so that the process window for aligning the floating gate with the active region of the cell is achieved with a relatively wide margin. Next, an oxide cap is formed over the floating gate. Using an oxide deposition method in place of the conventional polyoxidation method provides a less bulbous oxide formation over the floating gate, thus, yielding improved erase speed for the cell. The invention is also directed to a flash memory cell fabricated by the disclosed method.

摘要翻译： 提供了一种用于形成具有由CVD氧化物覆盖的非晶硅浮动栅极的闪存单元的方法，以及形成在氧化物盖上形成的栅间氧化物层上的控制栅极。 首先在衬底上的栅极氧化物层上形成无定形硅，随后在非晶硅层上形成氮化硅层。 将氮化硅图案化成具有锥形开口，使得用浮动栅极与电池的有源区对准的工艺窗口以相对较大的余量实现。 接下来，在浮动栅极上形成氧化物盖。 使用氧化物沉积方法代替常规的多氧化方法提供了在浮栅上的较少的氧化锆形成，从​​而产生改善的电池的擦除速度。 本发明还涉及通过所公开的方法制造的闪存单元。

公开(公告)号：US06358827B1

公开(公告)日：2002-03-19

申请号：US09764232

申请日：2001-01-19

申请人： Han-Ping Chen ,  Hung-Chen Sung ,  Cheng-Yuan Hsu

发明人： Han-Ping Chen ,  Hung-Chen Sung ,  Cheng-Yuan Hsu

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/28114 ,  H01L29/42376

摘要： A method is taught for forming a rectangular or near rectangular polysilicon sidewall structure, which can be used as an ultra narrow MOSFET gate electrode. The method employs the use a step on a sacrificial oxide against which the polysilicon sidewall is formed. An etch stop, such as a gate oxide is formed alongside the step. A polysilicon layer is deposited over the step followed by a silicon nitride layer. Next a flowable layer is deposited and cured. In a first embodiment the flowable layer is deposited to completely cover the polysilicon layer. Next the wafer is planarized to exposed the polysilicon layer over the high part of the step an to a level wherein the polysilicon/silicon nitride interface is driven away from the step to a distance which determines the final width of the final sidewall structure. The residual flowable layer is then removed and a silicon oxide hardmask is grown over the exposed polysilicon. The polysilicon is anisotropically etched, part way to the through and the hardmask is removed. Anisotropic etching is then continued until the etch stop and the top of the sacrificial oxide are exposed, leaving a polysilicon sidewall with a rectangular cross section. In a second embodiment, the flowable layer is deposited to partially fill the valley next to the step. The second embodiment, which is less complex than the first and does not employ planarization processing, forms a near rectangular sidewall structure with a curved top surface. This profile is useable in most sidewall polysilicon gate applications. The process is especially useful in split-gate flash memory applications.

摘要翻译： 教导了一种用于形成矩形或近似矩形的多晶硅侧壁结构的方法，其可以用作超窄MOSFET栅电极。 该方法采用在形成多晶硅侧壁的牺牲氧化物上使用台阶。 沿着台阶形成蚀刻停止物，例如栅极氧化物。 在该步骤之后沉积多晶硅层，接着是氮化硅层。 接下来，沉积和固化可流动层。 在第一实施例中，沉积可流动层以完全覆盖多晶硅层。 接下来，晶片被平坦化以将步骤a的高部分上的多晶硅层暴露于其中将多晶硅/氮化硅界面从该步骤驱动到一定距离，从而确定最终侧壁结构的最终宽度。 然后除去残留的可流动层，并在暴露的多晶硅上生长氧化硅硬掩模。 多晶硅被各向异性地蚀刻，部分途径到通孔，硬掩模被去除。 然后继续进行各向异性蚀刻，直到蚀刻停止和牺牲氧化物的顶部暴露，留下具有矩形横截面的多晶硅侧壁。 在第二实施例中，沉积可流动层以部分地填充步骤旁边的谷。 第二实施例，其比第一实施例不复杂并且不采用平面化处理，形成具有弯曲顶表面的接近矩形的侧壁结构。 该型材可用于大多数侧壁多晶硅栅极应用。 该过程在分闸门闪存应用中特别有用。

公开(公告)号：US08890230B2

公开(公告)日：2014-11-18

申请号：US13549510

申请日：2012-07-15

申请人： Cheng-Yuan Hsu ,  Chi Ren ,  Tzeng-Fei Wen

发明人： Cheng-Yuan Hsu ,  Chi Ren ,  Tzeng-Fei Wen

IPC分类号： H01L21/02

CPC分类号： H01L29/66825 ,  H01L21/266 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/7881 ,  H01L29/7882

摘要： A semiconductor device includes two floating gates, a control gate and a first dielectric layer. The floating gates are disposed on a semiconductor substrate. The control gate partially overlaps each of the floating gates, and a part of the control gate is disposed between the two floating gates. Furthermore, the first dielectric layer disposed between the two floating gates and the control gate has a fixed thickness.

摘要翻译： 半导体器件包括两个浮置栅极，控制栅极和第一介电层。 浮置栅极设置在半导体衬底上。 控制栅极部分地重叠每个浮置栅极，并且控制栅极的一部分设置在两个浮置栅极之间。 此外，设置在两个浮动栅极和控制栅极之间的第一介电层具有固定的厚度。

公开(公告)号：US07391073B2

公开(公告)日：2008-06-24

申请号：US11162497

申请日：2005-09-13

申请人： Tsung-Lung Chen ,  Hui-Hung Kuo ,  Cheng-Yuan Hsu ,  Chih-Wei Hung

发明人： Tsung-Lung Chen ,  Hui-Hung Kuo ,  Cheng-Yuan Hsu ,  Chih-Wei Hung

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/42324 ,  H01L27/115 ,  H01L27/11521

摘要： A method of fabricating a non-volatile memory is described. A substrate having a tunneling layer and a floating gate layer thereon is provided. A mask layer is formed on the floating gate. The mask layer has openings that expose a portion of the floating gate layer. Then, a portion of the floating gate layer is removed from the openings to form sunken regions on the surface of the floating gate layer. An inter-gate dielectric layer is formed on the floating gate layer. A control gate layer is formed on the inter-gate dielectric layer. After that, the mask layer and the floating gate layer under the mask layer are removed to form another opening. A select gate layer is formed inside the opening.

摘要翻译： 描述了制造非易失性存储器的方法。 提供了在其上具有隧道层和浮栅的衬底。 在浮动栅极上形成掩模层。 掩模层具有露出浮栅的一部分的开口。 然后，从开口去除浮栅的一部分，以在浮栅层的表面上形成凹陷区域。 栅极间介电层形成在浮栅层上。 在栅极间电介质层上形成控制栅极层。 之后，去除掩模层和掩模层下的浮栅层以形成另一个开口。 在开口内形成选择栅极层。

公开(公告)号：US20070128799A1

公开(公告)日：2007-06-07

申请号：US11669163

申请日：2007-01-31

申请人： Jui-Yu Pan ,  Cheng-Yuan Hsu ,  I-Chun Chuang ,  Chih-Wei Hung

发明人： Jui-Yu Pan ,  Cheng-Yuan Hsu ,  I-Chun Chuang ,  Chih-Wei Hung

IPC分类号： H01L21/336 ,  H01L29/94

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/7782

摘要： A method for fabricating a flash memory is described. A mask layer having openings to expose a portion of the substrate is formed on the substrate. A tunneling dielectric layer is formed at the bottom surface of the openings. Conductive spacers are formed on the sidewalls of the openings. The conductive spacers are patterned to form a plurality of floating gates. A plurality of buried doped regions is formed in the substrate under the bottom surface of the openings. An inter-gate dielectric layer is formed over the substrate. A plurality of control gates is formed over the substrate to fill the openings. The mask layer is removed to form a plurality of memory units. A plurality of source regions and drain regions are formed in the substrate beside the memory units.

摘要翻译： 描述了一种用于制造闪速存储器的方法。 在基板上形成具有露出基板的一部分的开口的掩模层。 在开口的底表面处形成隧道电介质层。 导电间隔件形成在开口的侧壁上。 将导电间隔物图案化以形成多个浮动栅极。 在开口底面下方的基板中形成多个掩埋掺杂区域。 栅极间电介质层形成在衬底上。 多个控制栅极形成在衬底上以填充开口。 去除掩模层以形成多个存储单元。 在存储单元旁边的基板中形成多个源极区域和漏极区域。

公开(公告)号：US20060205154A1

公开(公告)日：2006-09-14

申请号：US11308796

申请日：2006-05-05

申请人： Chih-Wei Hung ,  Cheng-Yuan Hsu

发明人： Chih-Wei Hung ,  Cheng-Yuan Hsu

IPC分类号： H01L21/336

CPC分类号： G11C16/0433 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/792

摘要： A non-volatile memory including a substrate, a plurality of gate structures, a plurality of select gate structures, spacers and source region/drain region is provided. Each gate structure on the substrate further includes a bottom dielectric layer, an electron trapping layer, an upper dielectric layer, a control gate and a cap layer. The select gate structures are disposed on one side of the respective each gate structure. Each select gate structure includes a select gate dielectric layer and a select gate. The select gate structures and the gate structures are connected in series to form a memory cell row. The spacers are disposed between the select gate structures and the gate structures. The source region and the drain region are disposed in the substrate on each side of the memory cell row.

摘要翻译： 提供了包括基板，多个栅极结构，多个选择栅极结构，间隔物和源极区域/漏极区域的非易失性存储器。 基板上的每个栅极结构还包括底部电介质层，电子俘获层，上介电层，控制栅极和盖层。 选择栅极结构设置在各个栅极结构的一侧。 每个选择栅极结构包括选择栅极电介质层和选择栅极。 选择栅极结构和栅极结构串联连接以形成存储单元行。 间隔件设置在选择栅极结构和栅极结构之间。 源极区域和漏极区域设置在存储单元行的每一侧的衬底中。

公开(公告)号：US06963105B2

公开(公告)日：2005-11-08

申请号：US10605419

申请日：2003-09-30

申请人： Chih-Wei Hung ,  Da Sung ,  Cheng-Yuan Hsu

发明人： Chih-Wei Hung ,  Da Sung ,  Cheng-Yuan Hsu

IPC分类号： G11C16/04 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L29/66825 ,  G11C16/0425 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/7885

摘要： A flash memory cell structure has a substrate, a select gate, a first-type doped region, a shallow second-type doped region, a deep second-type doped region, and a doped source region. The substrate has a stacked gate. The select gate is formed on the substrate and adjacent to the stacked gate. The first-type ion formed region is doped in the substrate and adjacent to the select gate as a drain. The shallow second-type doped region is formed on one side of the first-type doped region below the stacked gate. The deep second-type doped region, which serves as a well, is formed underneath the first-type doped region with one side bordering on the shallow second-type doped region. The doped source region is formed on a side of the shallow second-type doped region as a source.

摘要翻译： 闪存单元结构具有衬底，选择栅极，第一掺杂区域，浅第二掺杂区域，深第二掺杂区域和掺杂源极区域。 衬底具有堆叠栅极。 选择栅极形成在衬底上并且与堆叠栅极相邻。 第一离子形成区域在衬底中被掺杂并且与选择栅极相邻，作为漏极。 浅二次掺杂区形成在堆叠栅极下方的第一型掺杂区的一侧。 用作阱的深二次掺杂区形成在第一型掺杂区的下方，其中一侧与浅二次掺杂区接壤。 掺杂源区形成在浅二次掺杂区的一侧作为源。

公开(公告)号：US06737700B1

公开(公告)日：2004-05-18

申请号：US10249864

申请日：2003-05-13

申请人： Ko-Hsing Chang ,  Cheng-Yuan Hsu

发明人： Ko-Hsing Chang ,  Cheng-Yuan Hsu

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7883

摘要： A non-volatile memory cell having a symmetric cell structure is disclosed. The non-volatile memory cell includes a substrate, a tunnel oxide layer, two floating gates, a dielectric layer, a plurality of spacers, a control gate, and two split gates. The substrate has at least two sources and a drain that is located between the sources. The floating gates are formed on the tunneling oxide layer, and each of floating gates is located between each source and the drain. The dielectric layer is formed on the floating gates. The control gate is formed over the drain and is between the floating gates. The split gates are located adjacent to outward sidewalls of the floating gates, respectively. Therefore, each of the split gates is opposite to the control gate through each of the floating gates.

摘要翻译： 公开了具有对称单元结构的非易失性存储单元。 非易失性存储单元包括衬底，隧道氧化物层，两个浮动栅极，电介质层，多个间隔物，控制栅极和两个分离栅极。 衬底具有至少两个源和位于源之间的漏极。 浮动栅极形成在隧道氧化物层上，每个浮栅位于每个源极和漏极之间。 电介质层形成在浮栅上。 控制栅极形成在漏极之上并且在浮动栅极之间。 分流门分别位于浮动门的外侧壁附近。 因此，每个分离门通过每个浮动栅极与控制栅极相对。

公开(公告)号：US07485529B2

公开(公告)日：2009-02-03

申请号：US11621095

申请日：2007-01-08

申请人： Chih-Wei Hung ,  Cheng-Yuan Hsu ,  Da Sung

发明人： Chih-Wei Hung ,  Cheng-Yuan Hsu ,  Da Sung

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7923

摘要： A method of fabricating a non-volatile memory is described. A substrate having stacked gate structures thereon is provided. Each stacked gate structure includes a select gate dielectric layer, a select gate and a cap layer. A source region and a drain region are formed in the substrate. The source region and the drain region are separated from each other by at least two stacked gate structures. A tunneling dielectric layer is formed over the substrate and then a first conductive layer is formed over the tunneling dielectric layer. The first conductive layer is patterned to form floating gates in the gaps between the stacked gate structures. After forming an inter-gate dielectric layer over the substrate, a second conductive layer is formed over the substrate. The second conductive layer is patterned to form mutually linked control gates in the gaps between neighboring stacked gate structures.

摘要翻译： 描述了制造非易失性存储器的方法。 提供其上具有堆叠栅极结构的衬底。 每个堆叠栅极结构包括选择栅极介电层，选择栅极和盖层。 源极区和漏极区形成在衬底中。 源极区域和漏极区域通过至少两个堆叠的栅极结构彼此分离。 在衬底上形成隧穿电介质层，然后在隧道电介质层上形成第一导电层。 图案化第一导电层以在堆叠栅极结构之间的间隙中形成浮栅。 在衬底上形成栅极间电介质层之后，在衬底上形成第二导电层。 图案化第二导电层以在相邻的堆叠栅极结构之间的间隙中形成相互连接的控制栅极。