公开(公告)号：US07811890B2

公开(公告)日：2010-10-12

申请号：US11545575

申请日：2006-10-11

Applicant: Tzu-Hsuan Hsu ,  Yen-Hao Shih ,  Chia-Wei Wu

Inventor： Tzu-Hsuan Hsu ,  Yen-Hao Shih ,  Chia-Wei Wu

IPC: H01L21/336

CPC classification number: H01L29/792 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/42352

Abstract: A vertical channel transistor structure is provided. The structure includes a substrate, a channel, a cap layer, a charge trapping layer, a source and a drain. The channel is formed in a fin-shaped structure protruding from the substrate. The cap layer is deposited on the fin-shaped structure. The cap layer and the fin-shaped structure have substantially the same width. The charge trapping layer is deposited on the cap layer and on two vertical surfaces of the fin-shaped structure. The gate is deposited on the charge trapping layer and on two vertical surfaces of the fin-shaped structure. The source and the drain are respectively positioned on two sides of the fin-shaped structure and opposite the gate.

Abstract translation: 提供了垂直沟道晶体管结构。 该结构包括基板，通道，盖层，电荷捕获层，源极和漏极。 通道形成为从基板突出的鳍状结构。 盖层沉积在鳍状结构上。 盖层和鳍状结构具有基本上相同的宽度。 电荷俘获层沉积在盖层上和鳍状结构的两个垂直表面上。 栅极沉积在电荷捕获层上并在鳍状结构的两个垂直表面上沉积。 源极和漏极分别位于鳍状结构的两侧并与栅极相对。

公开(公告)号：US07495967B2

公开(公告)日：2009-02-24

申请号：US11601710

申请日：2006-11-20

Applicant: Chao-I Wu ,  Ming-Hsiu Lee ,  Tzu-Hsuan Hsu

Inventor： Chao-I Wu ,  Ming-Hsiu Lee ,  Tzu-Hsuan Hsu

IPC: G11C11/34

CPC classification number: G11C16/0475

Abstract: A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme.

Abstract translation: 公开了一种识别单元中的逻辑信息的方法，特别是在通过单孔读取方案通过热空穴注入氮化物电子存储（PHINES）单元编程中的方法。 该方法包括以下步骤：通过将局部阈值电压（Vt）增加到一定值来擦除PHINES单元的第一区域和第二区域; 通过热空穴注入来编程PHINES单元的第一区域和第二区域中的至少一个; 以及通过测量所述第一区域和所述第二区域之一的输出电流来读取所述PHINES单元的逻辑状态; 其中，通过存储在第一区域和第二区域中的不同量的热孔之间的相互作用引起不同量的输出电流，以便通过单面读取方案确定PHINES单元的逻辑状态。

公开(公告)号：US07474562B2

公开(公告)日：2009-01-06

申请号：US11292024

申请日：2005-12-01

Applicant: Ming-Chang Kuo ,  Chao-I Wu ,  Ming-Hsin Lee ,  Tzu-Hsuan Hsu

Inventor： Ming-Chang Kuo ,  Chao-I Wu ,  Ming-Hsin Lee ,  Tzu-Hsuan Hsu

IPC: G11C11/34

CPC classification number: G11C16/0466 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/7887 ,  H01L29/7923

Abstract: A method is provided of forming an assisted charge memory (AC-memory) cell. The method uses a two-sided charge trap memory cell that includes a two-sided charge trapping layer. A charge is formed in at least a portion of the two-sided charge trapping layer. One side (AC-side) of the two-sided charge trapping layer always has a fixed high threshold voltage (Vt) level which is the assisted charge for the AC-memory cell. The other side (data-side) is used for memory operations.

Abstract translation: 提供了形成辅助电荷存储器（AC-存储器）单元的方法。 该方法使用包括双面电荷捕获层的双面电荷陷阱存储单元。 在双面电荷俘获层的至少一部分中形成电荷。 双面电荷捕获层的一侧（AC侧）总是具有固定的高阈值电压（Vt）电平，其为AC存储单元的辅助电荷。 另一方（数据端）用于存储器操作。

公开(公告)号：US07450423B2

公开(公告)日：2008-11-11

申请号：US11649348

申请日：2007-01-03

Applicant: Erh-Kun Lai ,  Yen-Hao Shih ,  Tzu-Hsuan Hsu ,  Shih-Chih Lee ,  Jung-Yu Hsieh ,  Kuang-Yeu Hsieh

Inventor： Erh-Kun Lai ,  Yen-Hao Shih ,  Tzu-Hsuan Hsu ,  Shih-Chih Lee ,  Jung-Yu Hsieh ,  Kuang-Yeu Hsieh

IPC: G11C11/34 ,  G11C16/06 ,  H01L29/94

CPC classification number: H01L29/792 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/14 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/513

Abstract: A method of operating a memory cell by applying a positive voltage to the gate sufficient to cause hole tunneling from the gate toward the charge storage layer is disclosed. The method is applied to a memory cell including a semiconductor layer having at least two source/drain regions disposed below a surface of the semiconductor layer and separated by a channel region. The memory cell also has a lower insulating layer disposed above the channel region; a charge storage layer disposed above the lower insulating layer; an upper insulating multi-layer structure disposed above the charge storage layer. The upper insulating multi-layer structure comprises a lower dielectric layer and an upper nitride layer disposed above the lower dielectric layer and the memory cell has a gate disposed above the upper insulating multi-layer structure.

公开(公告)号：US20080251831A1

公开(公告)日：2008-10-16

申请号：US11786078

申请日：2007-04-10

Applicant: Chao-I Wu ,  Tzu-Hsuan Hsu

Inventor： Chao-I Wu ,  Tzu-Hsuan Hsu

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L29/792 ,  H01L27/115 ,  H01L27/11568

Abstract: A non-volatile memory cell capable of storing two bits of information having a non-conducting charge trapping dielectric, such as silicon nitride, layered in association with at least one electrical dielectric layer, such as an oxide, with a P-type substrate and an N-type channel implanted in the well region of the substrate between two source/drain regions is disclosed. The N-type channel achieves an inversion layer without the application of bias voltage to the gate of the memory cell. A method that implants the N-type channel in the P-type substrate of the cell wherein the N-type channel lowers the un-programmed or programmed voltage threshold of the memory cell to a value lower than would exist without the N-type channel is disclosed. The N-type channel reduces the second bit effect such that the window of operation between the programmed and un-programmed voltage thresholds of the bits is widened.

Abstract translation: 一种非易失性存储单元，其能够存储具有非导电电荷捕获电介质的两比特的信息，例如氮化硅，其与至少一个电介质层（例如氧化物）相关联地与P型衬底相结合，以及 公开了在两个源极/漏极区域之间植入衬底的阱区域中的N型沟道。 N型通道实现了反向层，而没有向存储单元的栅极施加偏置电压。 一种在单元的P型衬底中嵌入N型沟道的方法，其中N型沟道将存储单元的未编程或编程的电压阈值降低到低于不存在N型沟道的值 被披露。 N型通道减小了第二位效应，使得位的编程和非编程电压阈值之间的操作窗口变宽。

公开(公告)号：US20080227276A1

公开(公告)日：2008-09-18

申请号：US11686108

申请日：2007-03-14

Applicant: Gwo-Yuh Shiau ,  Ming Chyi Liu ,  Tzu-Hsuan Hsu ,  Chia-Shiung Tsai

Inventor： Gwo-Yuh Shiau ,  Ming Chyi Liu ,  Tzu-Hsuan Hsu ,  Chia-Shiung Tsai

IPC: H01L21/22

CPC classification number: H01L21/268 ,  H01L27/1464 ,  H01L27/14683

Abstract: The present disclosure provides a method for fabricating a semiconductor device including providing a semiconductor substrate comprising a first surface and a second surface, wherein at least one imaging sensor is located adjacent the first surface, activating a dopant layer in the semiconductor substrate adjacent the second surface using a localized annealing process, and etching the dopant layer

Abstract translation: 本公开提供一种制造半导体器件的方法，包括提供包括第一表面和第二表面的半导体衬底，其中至少一个成像传感器位于第一表面附近，激活邻近第二表面的半导体衬底中的掺杂剂层 使用局部退火工艺，并蚀刻掺杂剂层

公开(公告)号：US20080191296A1

公开(公告)日：2008-08-14

申请号：US11672681

申请日：2007-02-08

Applicant: Wen-De Wang ,  Dun-Nian Yaung ,  Tzu-Hsuan Hsu ,  Shine Chung

Inventor： Wen-De Wang ,  Dun-Nian Yaung ,  Tzu-Hsuan Hsu ,  Shine Chung

IPC: H01L31/0232 ,  H01L31/18

CPC classification number: H01L27/14632 ,  H01L27/14625 ,  H01L27/14687

Abstract: The present disclosure provides an image sensor semiconductor device. The semiconductor device includes a sensor element disposed in a semiconductor substrate; an inter-level dielectric (ILD) disposed on the semiconductor substrate; and a trench disposed in the ILD, overlying and enclosing the sensor element, and filled with a first dielectric material.

Abstract translation: 本公开提供了一种图像传感器半导体器件。 半导体器件包括设置在半导体衬底中的传感器元件; 布置在所述半导体衬底上的级间电介质（ILD）; 以及设置在ILD中的沟槽，覆盖并封闭传感器元件，并且填充有第一介电材料。

公开(公告)号：US20080173963A1

公开(公告)日：2008-07-24

申请号：US11626757

申请日：2007-01-24

Applicant: Tzu-Hsuan Hsu ,  Shou-Gwo Wuu ,  Dun-Nian Yaung

Inventor： Tzu-Hsuan Hsu ,  Shou-Gwo Wuu ,  Dun-Nian Yaung

IPC: H01L27/14

CPC classification number: H01L27/1463 ,  H01L27/1464 ,  H01L27/14683

Abstract: The present disclosure provides a backside illuminated semiconductor device. The device includes a substrate having a front surface and a back surface; a plurality of sensor elements formed in the substrate, each of the plurality of sensor elements is designed and configured to receive light directed towards the back surface; and a sensor isolation feature formed in the substrate, and disposed horizontally between two adjacent elements of the plurality of sensor elements, and vertically between the back surface and the front surface.

Abstract translation: 本公开提供了背面照明半导体器件。 该装置包括具有前表面和后表面的基板; 形成在所述基板中的多个传感器元件，所述多个传感器元件中的每一个被设计和配置成接收朝向所述后表面的光; 以及形成在所述基板中的传感器隔离特征，并且水平地设置在所述多个传感器元件的两个相邻元件之间，并且在所述后表面和所述前表面之间垂直。

公开(公告)号：US20080087942A1

公开(公告)日：2008-04-17

申请号：US11785322

申请日：2007-04-17

Applicant: Tzu-Hsuan Hsu ,  Hang-Ting Lue

Inventor： Tzu-Hsuan Hsu ,  Hang-Ting Lue

IPC: H01L29/792 ,  G11C11/34 ,  H01L21/336

CPC classification number: H01L29/66833 ,  G11C16/0466 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/785 ,  H01L29/792

Abstract: A vertical channel memory including a substrate, a channel, a multi-layer structure, a gate, a first terminal and a second terminal is provided. The channel is protruded from the substrate and has a top surface and two vertical surfaces. The multi-layer structure is disposed on the two vertical surfaces of the channel. The gate straddling multi-layer structure is positioned above the two vertical surfaces of the channel. The first terminal and the second terminal are respectively positioned at two sides of the channel opposing to the gate.

Abstract translation: 提供了包括基板，通道，多层结构，栅极，第一端子和第二端子的垂直沟道存储器。 通道从基板突出并具有顶表面和两个垂直表面。 多层结构设置在通道的两个垂直表面上。 栅极跨层多层结构位于通道的两个垂直表面上方。 第一端子和第二端子分别位于与栅极相对的通道的两侧。

公开(公告)号：US07355897B2

公开(公告)日：2008-04-08

申请号：US11773857

申请日：2007-07-05

Applicant: Tzu-Hsuan Hsu ,  Yen-Hao Shih

Inventor： Tzu-Hsuan Hsu ,  Yen-Hao Shih

IPC: G11C16/04

CPC classification number: G11C16/0475

Abstract: A method for operating a nitride trapping memory cell is provided to resolve hard-to-erase condition by employing a reset technique to eliminate or reduce the number of electrons in the middle of a junction region. When a hard-to-erase condition is detected after a series of program and erase cycles, such as 500 or 100 program and erase cycles, a substrate transient hot hole (STHH) reset operation is applied. The substrate transient hot hole reset injects holes that are far away junction than band-to-band tunneling hot hole (BTBTHH) injection such that the STHH reset on cycle endurance is able to maintain a desirable cycle window to eliminate or reduce the hard-to erase condition in subsequent program and erase cycles.

Abstract translation: 提供了一种操作氮化物捕获存储单元的方法，通过采用复位技术来消除或减少接合区中间的电子数量来解决硬擦除条件。 当在一系列编程和擦除周期（例如500或100个编程和擦除周期）之后检测到难以擦除的条件时，应用基板瞬态热孔（STHH）复位操作。 衬底瞬态热孔复位注入与带 - 带隧道热孔（BTBTHH）注入相距较远的结的孔，使得周期耐久下的STHH复位能够保持期望的循环窗口以消除或减少难以 随后的编程和擦除周期中的擦除条件。