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231 条记录 (耗时 0.035 秒)

    Integrated Circuit Diode
    81.
    发明申请
    Integrated Circuit Diode 有权
    集成电路二极管

    公开(公告)号：US20120286364A1

    公开(公告)日：2012-11-15

    申请号：US13104542

    申请日：2011-05-10

    申请人： Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    发明人： Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    IPC分类号： H01L27/12 ,  H01L21/8238

    CPC分类号： H01L27/0727 ,  H01L21/823418 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203

    摘要： A method includes forming isolation regions in a semiconductor substrate to define a first field effect transistor (FET) region, a second FET region, and a diode region, forming a first gate stack in the first FET region and a second gate stack in the second FET region, forming a layer of spacer material over the second FET region and the second gate stack, forming a first source region and a first drain region in the first FET region and a first diode layer in the diode region using a first epitaxial growth process, forming a hardmask layer over the first source region, the first drain region, the first gate stack and a portion of the first diode layer, and forming a second source region and a second drain region in the first FET region and a second diode layer on the first diode layer using a second epitaxial growth process.

    摘要翻译： 一种方法包括在半导体衬底中形成隔离区以限定第一场效应晶体管（FET）区域，第二FET区域和二极管区域，在第一FET区域中形成第一栅极堆叠，在第二FET区域中形成第二栅极堆叠 FET区域，在所述第二FET区域和所述第二栅极堆叠上形成间隔材料层，在所述第一FET区域中形成第一源极区域和第一漏极区域，以及使用第一外延生长工艺在所述二极管区域中形成第一二极管层 在所述第一源极区域，所述第一漏极区域，所述第一栅极堆叠层和所述第一二极管层的一部分上形成硬掩模层，以及在所述第一FET区域中形成第二源极区域和第二漏极区域，以及在所述第一FET区域中形成第二二极管层 使用第二外延生长工艺在第一二极管层上。

    HYBRID MOSFET STRUCTURE HAVING DRAIN SIDE SCHOTTKY JUNCTION
    85.
    发明申请
    HYBRID MOSFET STRUCTURE HAVING DRAIN SIDE SCHOTTKY JUNCTION 有权
    具有排水侧肖特基结的混合MOSFET结构

    公开(公告)号：US20120235239A1

    公开(公告)日：2012-09-20

    申请号：US13049491

    申请日：2011-03-16

    申请人： Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    发明人： Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    IPC分类号： H01L27/12 ,  H01L21/336 ,  H01L29/78

    CPC分类号： H01L21/84 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/7839

    摘要： A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate, forming a raised source region over the semiconductor substrate adjacent a source side of the gate structure, and forming silicide contacts on the raised source region, on the patterned gate structure, and on the semiconductor substrate adjacent a drain side of the gate structure. Thereby, a hybrid field effect transistor (FET) structure having a drain side Schottky contact and a raised source side ohmic contact is defined.

    摘要翻译： 一种形成晶体管器件的方法包括在半导体衬底上形成图案化的栅极结构，在邻近栅极结构的源极侧的半导体衬底上形成凸起的源极区域，并在图案化的栅极上形成凸起的源极区域上的硅化物接触 并且在与栅极结构的漏极侧相邻的半导体衬底上。 因此，限定了具有漏极侧肖特基接触和升高的源极侧欧姆接触的混合场效应晶体管（FET）结构。

    Hybrid FinFET/planar SOI FETs
    86.
    发明授权
    Hybrid FinFET/planar SOI FETs 有权
    混合FinFET /平面SOI FET

    公开(公告)号：US08138543B2

    公开(公告)日：2012-03-20

    申请号：US12621460

    申请日：2009-11-18

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ghavam G. Shahidi

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ghavam G. Shahidi

    IPC分类号： H01L27/01

    CPC分类号： H01L21/845 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1211 ,  H01L29/785

    摘要： A circuit structure is disclosed which contains least one each of three different kinds of devices in a silicon layer on insulator (SOI): a planar NFET device, a planar PFET device, and a FinFET device. A trench isolation surrounds the planar NFET device and the planar PFET device penetrating through the SOI and abutting the insulator. Each of the three different kinds of devices contain a high-k gate dielectric layer and a mid-gap gate metal layer, each containing an identical high-k material and an identical mid-gap metal. Each of the three different kinds of devices have an individually optimized threshold value. A method for fabricating a circuit structure is also disclosed, which method involves defining portions in SOI respectively for three different kinds of devices: for a planar NFET device, for a planar PFET device, and for a FinFET device. The method also includes depositing in common a high-k gate dielectric layer and a mid-gap gate metal layer, and using workfunction modifying layers to individually adjust thresholds for the various kinds of devices.

    摘要翻译： 公开了一种电路结构，其包含绝缘体上硅层（SOI）中的三种不同类型的器件中的至少一种：平面NFET器件，平面PFET器件和FinFET器件。 沟槽隔离围绕平面NFET器件，并且平面PFET器件穿透SOI并邻接绝缘体。 三种不同类型的器件中的每一种都包含高k栅极电介质层和中间间隙栅极金属层，每个包含相同的高k材料和相同的中间间隙金属。 三种不同类型的设备中的每一种具有单独优化的阈值。 还公开了一种用于制造电路结构的方法，该方法包括为三种不同类型的器件分别定义SOI中的部分：对于平面NFET器件，用于平面PFET器件和FinFET器件。 该方法还包括共同沉积高k栅极电介质层和中间间隙栅极金属层，并且使用功函数修改层来单独调节各种器件的阈值。

    Same-Chip Multicharacteristic Semiconductor Structures
    87.
    发明申请
    Same-Chip Multicharacteristic Semiconductor Structures 有权
    同芯多特征半导体结构

    公开(公告)号：US20120049284A1

    公开(公告)日：2012-03-01

    申请号：US12861976

    申请日：2010-08-24

    申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

    IPC分类号： H01L27/12 ,  H01L21/336

    CPC分类号： H01L27/1211 ,  H01L27/1203

    摘要： In one exemplary embodiment, a semiconductor structure includes: a semiconductor-on-insulator substrate with a top semiconductor layer overlying an insulation layer and the insulation layer overlies a bottom substrate layer; at least one first device at least partially overlying and disposed upon a first portion of the top semiconductor layer, where the first portion has a first thickness, a first width and a first depth; and at least one second device at least partially overlying and disposed upon a second portion of the top semiconductor layer, where the second portion has a second thickness, a second width and a second depth, where at least one of the following holds: the first thickness is greater than the second thickness, the first width is greater than the second width and the first depth is greater than the second depth.

    摘要翻译： 在一个示例性实施例中，半导体结构包括：绝缘体上半导体衬底，具有覆盖绝缘层的顶部半导体层，绝缘层覆盖在底部衬底层上; 至少一个第一装置至少部分地覆盖并设置在顶部半导体层的第一部分上，其中第一部分具有第一厚度，第一宽度和第一深度; 以及至少一个第二装置，其至少部分地覆盖并设置在顶部半导体层的第二部分上，其中第二部分具有第二厚度，第二宽度和第二深度，其中以下至少一个成立：第一 厚度大于第二厚度，第一宽度大于第二宽度，第一深度大于第二深度。

    Extremely thin silicon on insulator (ETSOI) complementary metal oxide semiconductor (CMOS) with in-situ doped source and drain regions formed by a single mask
    88.
    发明授权
    Extremely thin silicon on insulator (ETSOI) complementary metal oxide semiconductor (CMOS) with in-situ doped source and drain regions formed by a single mask 有权
    非常薄的绝缘体上硅（ETSOI）互补金属氧化物半导体（CMOS），其具有由单个掩模形成的原位掺杂源极和漏极区域

    公开(公告)号：US08084309B2

    公开(公告)日：2011-12-27

    申请号：US12542179

    申请日：2009-08-17

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ghavam G. Shahidi

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ghavam G. Shahidi

    IPC分类号： H01L21/00 ,  H01L21/84

    CPC分类号： H01L21/84 ,  H01L21/823814 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

    摘要： A method of fabricating an electronic structure is provided that includes forming a first conductivity doped first semiconductor material on the SOI semiconductor layer of a substrate. The SOI semiconductor layer has a thickness of less than 10 nm. The first conductivity in-situ doped first semiconductor material is removed from a first portion of the SOI semiconductor layer, wherein a remaining portion of the first conductivity in-situ doped first semiconductor material is present on a second portion of SOI semiconductor layer. A second conductivity in-situ doped second semiconductor material is formed on the first portion of the SOI semiconductor layer, wherein a mask prohibits the second conductivity in-situ doped semiconductor material from being formed on the second portion of the SOI semiconductor layer. The dopants from the first and second conductivity in-situ doped semiconductor materials are diffused into the first semiconductor layer to form dopant regions.

    摘要翻译： 提供一种制造电子结构的方法，其包括在衬底的SOI半导体层上形成第一导电掺杂的第一半导体材料。 SOI半导体层的厚度小于10nm。 第一导电性原位掺杂的第一半导体材料从SOI半导体层的第一部分去除，其中第一导电性原位掺杂的第一半导体材料的剩余部分存在于SOI半导体层的第二部分上。 第二导电性原位掺杂的第二半导体材料形成在SOI半导体层的第一部分上，其中掩模禁止在SOI半导体层的第二部分上形成第二导电性原位掺杂半导体材料。 来自第一和第二导电性原位掺杂半导体材料的掺杂剂扩散到第一半导体层中以形成掺杂区域。

    TUNNEL FIELD EFFECT TRANSISTOR
    90.
    发明申请
    TUNNEL FIELD EFFECT TRANSISTOR 有权
    隧道场效应晶体管

    公开(公告)号：US20110254080A1

    公开(公告)日：2011-10-20

    申请号：US12760287

    申请日：2010-04-14

    申请人： Bruce B. Doris ,  Kangguo Cheng ,  Wilfried E. Haensch ,  Ali Khakifirooz ,  Isaac Lauer ,  Ghavam G. Shahidi

    发明人： Bruce B. Doris ,  Kangguo Cheng ,  Wilfried E. Haensch ,  Ali Khakifirooz ,  Isaac Lauer ,  Ghavam G. Shahidi

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L21/26586 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/78

    摘要： A method for fabricating an FET device characterized as being a tunnel FET (TFET) device is disclosed. The method includes processing a gate-stack, and processing the adjoining source and drain junctions, which are of a first conductivity type. A hardmask is formed covering the gate-stack and the junctions. A tilted angle ion implantation is performed which is received by a first portion of the hardmask, and it is not received by a second portion of the hardmask due to the shadowing of the gate-stack. The implanted portion of the hardmask is removed and one of the junctions is exposed. The junction is etched away, and a new junction, typically in-situ doped to a second conductivity type, is epitaxially grown into its place. A device characterized as being an asymmetrical TFET is also disclosed. The source and drain junctions of the TFET are of different conductivity types, and the TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side of the gate-stack.

    摘要翻译： 公开了一种用于制造FET器件的方法，其特征在于是隧道FET（TFET）器件。 该方法包括处理栅极堆叠，以及处理第一导电类型的邻接的源极和漏极结。 形成覆盖栅极堆叠和结的硬掩模。 执行由硬掩模的第一部分接收的倾斜角度离子注入，并且由于栅极堆叠的阴影而不被硬掩模的第二部分接收。 去除硬掩模的注入部分，并露出其中一个接头。 该结被蚀刻掉，并且通常原位掺杂到第二导电类型的新结，外延生长到其位置。 还公开了一种特征为不对称TFET的器件。 TFET的源极和漏极结具有不同的导电类型，并且TFET还包括间隔物结构，使得栅极堆叠的一侧上的间隔物形成比栅极堆叠的另一侧更薄。