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    METAL ION TRANSISTOR AND RELATED METHODS
    81.
    发明申请
    METAL ION TRANSISTOR AND RELATED METHODS 有权
    金属离子晶体管及相关方法

    公开(公告)号：US20090146242A1

    公开(公告)日：2009-06-11

    申请号：US11951579

    申请日：2007-12-06

    申请人： Fen Chen ,  Armin Fischer

    发明人： Fen Chen ,  Armin Fischer

    IPC分类号： H01L29/00 ,  H01L21/425

    CPC分类号： H01L45/00

    摘要： A metal ion transistor and related methods are disclosed. In one embodiment, the metal ion transistor includes a cell positioned in at least one isolation layer, the cell including a metal ion doped low dielectric constant (low-k) dielectric material sealed from each adjacent isolation layer; a first electrode contacting the cell on a first side; a second electrode contacting the cell on a second side; and a third electrode contacting the cell on a third side, wherein each electrode is isolated from each other electrode.

    摘要翻译： 公开了一种金属离子晶体管及相关方法。 在一个实施例中，金属离子晶体管包括位于至少一个隔离层中的电池，该电池包括从每个相邻隔离层密封的金属离子掺杂低介电常数（低k）电介质材料; 在第一侧上与第一电极接触的第一电极; 在第二侧接触所述电池的第二电极; 以及在第三侧与第一电极接触的第三电极，其中每个电极彼此隔离。

    NON-DESTRUCTIVE EVALUATION OF MICROSTRUCTURE AND INTERFACE ROUGHNESS OF ELECTRICALLY CONDUCTING LINES IN SEMICONDUCTOR INTEGRATED CIRCUITS IN DEEP SUB-MICRON REGIME
    83.
    发明申请
    NON-DESTRUCTIVE EVALUATION OF MICROSTRUCTURE AND INTERFACE ROUGHNESS OF ELECTRICALLY CONDUCTING LINES IN SEMICONDUCTOR INTEGRATED CIRCUITS IN DEEP SUB-MICRON REGIME 有权
    深层次微电解法半导体集成电路中导电线路的微结构和界面粗糙度的非破坏性评估

    公开(公告)号：US20070130551A1

    公开(公告)日：2007-06-07

    申请号：US11673369

    申请日：2007-02-09

    申请人： Fen Chen ,  Jeffrey Gambino ,  Jason Gill ,  Baozhen Li ,  Timothy Sullivan

    发明人： Fen Chen ,  Jeffrey Gambino ,  Jason Gill ,  Baozhen Li ,  Timothy Sullivan

    IPC分类号： G06F17/50

    CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Novel structures and methods for evaluating lines in semiconductor integrated circuits. A first plurality of lines are formed on a wafer each of which includes multiple line sections. All the line sections are of the same length. The electrical resistances of the line sections are measured. Then, a first line geometry adjustment is determined based on the electrical resistances of all the sections. The first line geometry adjustment represents an effective reduction of cross-section size of the lines due to grain boundary electrical resistance. A second plurality of lines of same length and thickness can be formed on the same wafer. Then, second and third line geometry adjustments are determined based on the electrical resistances of these lines measured at different temperatures. The second and third line geometry adjustments represent an effective reduction of cross-section size of the lines due to grain boundary electrical resistance and line surface roughness.

    摘要翻译： 用于评估半导体集成电路中的线路的新型结构和方法。 在每个包括多个线段的晶片上形成第一组多条线。 所有线段长度相同。 测量线路段的电阻。 然后，基于所有部分的电阻来确定第一行几何调整。 第一行几何调整表示由于晶界电阻而导致的线的横截面尺寸的有效减小。 相同长度和厚度的第二组多条线可以形成在同一晶片上。 然后，基于在不同温度下测量的这些线的电阻来确定第二和第三线几何调整。 第二和第三线几何调整表示由于晶界电阻和线表面粗糙度导致的线的横截面尺寸的有效减小。

    OPTOELECTRONIC MEMORY DEVICES
    84.
    发明申请
    OPTOELECTRONIC MEMORY DEVICES 失效
    光电存储器件

    公开(公告)号：US20070051875A1

    公开(公告)日：2007-03-08

    申请号：US11161941

    申请日：2005-08-23

    申请人： Fen Chen ,  Richard Kontra ,  Tom Lee ,  Theodore Levin ,  Christopher Muzzy ,  Timothy Sullivan

    发明人： Fen Chen ,  Richard Kontra ,  Tom Lee ,  Theodore Levin ,  Christopher Muzzy ,  Timothy Sullivan

    IPC分类号： H01J40/14 ,  H01L31/00

    CPC分类号： G11C13/0009 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/04 ,  G11C13/047 ,  G11C2013/0054 ,  H01L45/1213 ,  H01L45/145

    摘要： A structure and a method for operating the same. The method comprises providing a resistive/reflective region on a substrate, wherein the resistive/reflective region comprises a material having a characteristic of changing the material's reflectance due to the material absorbing heat; sending an electric current through the resistive/reflective region so as to cause a reflectance change in the resistive/reflective region from a first reflectance value to a second reflectance value different from the first reflectance value; and optically reading the reflectance change in the resistive/reflective region.

    摘要翻译： 一种结构及其操作方法。 该方法包括在衬底上提供电阻/反射区域，其中电阻/反射区域包括具有由于材料吸收热而改变材料的反射率的特性的材料; 发送电流通过电阻/反射区域，以使电阻/反射区域的反射率变化从第一反射率值到不同于第一反射率值的第二反射率值; 并且光学地读取电阻/反射区域中的反射率变化。

    THERMO-MECHANICAL CLEAVABLE STRUCTURE
    85.
    发明申请
    THERMO-MECHANICAL CLEAVABLE STRUCTURE 有权
    热机械可靠结构

    公开(公告)号：US20060163685A1

    公开(公告)日：2006-07-27

    申请号：US10905905

    申请日：2005-01-26

    申请人： Fen Chen ,  Cathryn Christiansen ,  Richard Kontra ,  Tom Lee ,  Alvin Strong ,  Timothy Sullivan ,  Joseph Therrien

    发明人： Fen Chen ,  Cathryn Christiansen ,  Richard Kontra ,  Tom Lee ,  Alvin Strong ,  Timothy Sullivan ,  Joseph Therrien

    IPC分类号： H01L29/00 ,  H01L21/00

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A thermo-mechanical cleavable structure is provided and may be used as a programmable fuse for integrated circuits. As applied to a programmable fuse, the thermo-mechanical cleavable structure includes an electrically conductive cleavable layer adjacent to a thermo-mechanical stressor. As electricity is passed through the cleavable layer, the cleavable layer and the thermo-mechanical stressor are heated and gas evolves from the thermo-mechanical stressor. The gas locally insulates the thermo-mechanical stressor, causing local melting adjacent to the bubbles in the thermo-mechanical stressor and the cleavable structure forming cleaving sites. The melting also interrupts the current flow through the cleavable structure so the cleavable structure cools and contracts. The thermo-mechanical stressor also contracts due to a phase change caused by the evolution of gas therefrom. As the thermo-mechanical cleavable structure cools, the cleaving sites expand causing gaps to be permanently formed therein.

    摘要翻译： 提供了一种热机械可切割结构，可用作集成电路的可编程保险丝。 如应用于可编程保险丝，热机械可切割结构包括与热机械应力源相邻的导电可切割层。 当电通过可切割层时，可切割层和热机械应力器被加热并且气体从热机械应力源逸出。 气体将热机械应力局部绝缘，导致邻近热机械应力的气泡局部熔化，形成裂开位置的可切割结构。 熔化还中断当前通过可切割结构的流动，因此可切割结构冷却和收缩。 热机械应力还由于由其产生的气体引起的相变而收缩。 当热机械可裂解结构冷却时，裂解位置膨胀，导致间隙永久形成。

    NON-DESTRUCTIVE EVALUATION OF MICROSTRUCTURE AND INTERFACE ROUGHNESS OF ELECTRICALLY CONDUCTING LINES IN SEMICONDUCTOR INTEGRATED CIRCUITS IN DEEP SUB-MICRON REGIME
    86.
    发明申请
    NON-DESTRUCTIVE EVALUATION OF MICROSTRUCTURE AND INTERFACE ROUGHNESS OF ELECTRICALLY CONDUCTING LINES IN SEMICONDUCTOR INTEGRATED CIRCUITS IN DEEP SUB-MICRON REGIME 有权
    深层次微电解法半导体集成电路中导电线路的微结构和界面粗糙度的非破坏性评估

    公开(公告)号：US20060071676A1

    公开(公告)日：2006-04-06

    申请号：US10711418

    申请日：2004-09-17

    申请人： Fen Chen ,  Jeffrey Gambino ,  Jason Gill ,  Baozhen Li ,  Timothy Sullivan

    发明人： Fen Chen ,  Jeffrey Gambino ,  Jason Gill ,  Baozhen Li ,  Timothy Sullivan

    IPC分类号： G01R31/26

    CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Novel structures and methods for evaluating lines in semiconductor integrated circuits. A first plurality of lines can be formed on a wafer each of which comprises multiple line sections. All the line sections are of the same length. The electrical resistances of the line sections are measured. Then, a first line geometry adjustment is determined based on the electrical resistances of all the sections of all the lines. The first line geometry adjustment represents an effective reduction of cross-section size of the lines due to grain boundary electrical resistance. A second plurality of lines of same length and thickness can be formed on the same wafer. Then, second and third line geometry adjustments can be determined based on the electrical resistances of these lines measured at different temperatures. The second and third line geometry adjustments represent an effective reduction of cross-section size of the lines due to grain boundary electrical resistance and line surface roughness.

    摘要翻译： 用于评估半导体集成电路中的线路的新型结构和方法。 可以在每个包括多个线段的晶片上形成第一组多条线。 所有线段长度相同。 测量线路段的电阻。 然后，基于所有线的所有部分的电阻来确定第一线几何形状调整。 第一行几何调整表示由于晶界电阻而导致的线的横截面尺寸的有效减小。 相同长度和厚度的第二组多条线可以形成在同一晶片上。 然后，可以基于在不同温度下测量的这些线的电阻来确定第二和第三线几何调整。 第二和第三线几何调整表示由于晶界电阻和线表面粗糙度导致的线的横截面尺寸的有效减小。