公开(公告)号：US20070108638A1

公开(公告)日：2007-05-17

申请号：US11164266

申请日：2005-11-16

Applicant: Michael Lane ,  Christopher Muzzy ,  Roger Yerdon

Inventor： Michael Lane ,  Christopher Muzzy ,  Roger Yerdon

IPC: H01L23/544 ,  H01L21/78

CPC classification number: H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A robust alignment mark used in semiconductor processing to help deter the expansion of cracks and delamination caused by the cutting of a dicing blade. A cross-shaped structure is used as a line site for alignment of the dicing blade. A plurality of rectangular elements is situated about the periphery of the alignment mark and populated with via bar structures that are interconnected at each level of the wafer, and laid in a serpentine fashion throughout each element to expose more of the via bar structure surface area to propagating cracks. The rectangular elements are formed of different sizes to expose more surface area to propagating cracks. A plurality of square, metal-level structures is formed in the area between the cross-shaped structure and the peripherally placed, rectangular elements.

Abstract translation: 在半导体处理中使用的坚固的对准标记，以帮助阻止由切割刀片切割引起的裂纹和分层的扩展。 十字形结构被用作对准切割刀片的线状部位。 多个矩形元件围绕对准标记的周边设置，并且填充有在每个晶片的每个级别处互连的通孔条结构，并且遍及每个元件以蛇形方式铺设以将更多的通孔条结构表面区域暴露于 传播裂缝。 矩形元件由不同的尺寸形成，以使更多的表面积暴露于传播的裂纹。 在十字形结构和外围放置的矩形元件之间的区域中形成多个方形金属层结构。

公开(公告)号：US20050077593A1

公开(公告)日：2005-04-14

申请号：US10605617

申请日：2003-10-14

Applicant: William Motsiff ,  Christopher Muzzy

Inventor： William Motsiff ,  Christopher Muzzy

IPC: H01L23/525 ,  H01L27/10

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and associated method for protecting an electrical structure during a fuse link deletion by focused radiation. The structure comprises a fuse element, a protection plate, a first dielectric layer, and a second dielectric layer. The structure is formed within a semiconductor device. The protection plate is formed within the first dielectric layer using a damascene process. The second dielectric layer is formed over the protection plate and the first dielectric layer. The fuse element is formed over the second dielectric layer. The fuse element is adapted to be cut with a laser beam. The dielectric constant of the second dielectric layer is greater than the dielectric constant of the first dielectric layer. The protection plate is adapted to shield the first dielectric layer from energy from the laser beam.

Abstract translation: 一种用于通过聚焦辐射在熔断体缺失期间保护电气结构的结构和相关方法。 该结构包括熔丝元件，保护板，第一电介质层和第二电介质层。 该结构形成在半导体器件内。 使用镶嵌工艺在第一介电层内形成保护板。 第二电介质层形成在保护板和第一介电层上。 熔丝元件形成在第二介电层上。 熔丝元件适于用激光束切割。 第二电介质层的介电常数大于第一介电层的介电常数。 保护板适于屏蔽来自激光束的能量的第一介电层。

公开(公告)号：US07704804B2

公开(公告)日：2010-04-27

申请号：US11953363

申请日：2007-12-10

Applicant: Timothy Daubenspeck ,  Jeffrey Gambino ,  Christopher Muzzy ,  Wolfgang Sauter

Inventor： Timothy Daubenspeck ,  Jeffrey Gambino ,  Christopher Muzzy ,  Wolfgang Sauter

IPC: H01L21/82

CPC classification number: H01L23/5258 ,  H01L23/585 ,  H01L24/02 ,  H01L24/03 ,  H01L24/12 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2224/05552

Abstract: A crack stop void is formed in a low-k dielectric or silicon oxide layer between adjacent fuse structures for preventing propagation of cracks between the adjacent fuse structures during a fuse blow operation. The passivation layer is fixed in place by using an etch stop shape of conducting material which is formed simultaneously with the formation of the interconnect structure. This produces a reliable and repeatable fuse structure that has controllable passivation layer over the fuse structure that is easily manufactured.

Abstract translation: 在相邻熔丝结构之间的低k电介质或氧化硅层中形成裂纹阻挡空隙，用于在保险丝熔断操作期间防止相邻熔丝结构之间的裂纹传播。 通过使用与形成互连结构同时形成的导电材料的蚀刻停止形状将钝化层固定就位。 这产生了可靠且可重复的熔丝结构，其在容易制造的熔丝结构上具有可控钝化层。

公开(公告)号：US20070200229A1

公开(公告)日：2007-08-30

申请号：US11276380

申请日：2006-02-27

Applicant: Timothy Daubenspeck ,  Jeffrey Gambino ,  Christopher Muzzy ,  Wolfgang Sauter ,  David Questad

Inventor： Timothy Daubenspeck ,  Jeffrey Gambino ,  Christopher Muzzy ,  Wolfgang Sauter ,  David Questad

IPC: H01L21/50 ,  H01L23/34

CPC classification number: H01L21/563 ,  H01L23/3128 ,  H01L24/10 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/14 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81194 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83194 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/3512

Abstract: A semiconductor structure and method for forming the same. The semiconductor structure includes (a) a substrate and (b) a chip which includes N chip solder balls, N is a positive integer, and the N chip solder balls are in electrical contact with the substrate. The semiconductor structure further includes (c) first, second, third, and fourth corner underfill regions which are respectively at first, second, third, and fourth corners of the chip, and sandwiched between the chip and the substrate. The semiconductor structure further includes (d) a main underfill region sandwiched between the chip and the substrate. The first, second, third, and fourth corner underfill regions, and the main underfill region occupy essentially an entire space between the chip and the substrate. A corner underfill material of the first, second, third, and fourth corner underfill regions is different from a main underfill material of the main underfill region.

Abstract translation: 一种半导体结构及其形成方法。 半导体结构包括（a）基板和（b）包括N个芯片焊球，N是正整数的芯片，并且N个芯片焊球与基板电接触。 半导体结构还包括（c）分别在芯片的第一，第二，第三和第四角部处并夹在芯片和基板之间的第一，第二，第三和第四角底部填充区域。 半导体结构还包括（d）夹在芯片和衬底之间的主要底部填充区域。 第一，第二，第三和第四角底部填充区域，并且主底部填充区域基本上占据芯片和基板之间的整个空间。 第一，第二，第三和第四角底部填充区域的角底层填充材料与主要底部填充区域的主要底部填充材料不同。

公开(公告)号：US20070176288A1

公开(公告)日：2007-08-02

申请号：US11275867

申请日：2006-02-01

Applicant: Timothy Daubenspeck ,  Jeffrey Gambino ,  Christopher Muzzy ,  Wolfgang Sauter

Inventor： Timothy Daubenspeck ,  Jeffrey Gambino ,  Christopher Muzzy ,  Wolfgang Sauter

IPC: H01L23/48

CPC classification number: H01L24/13 ,  H01L23/562 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15787 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A structure and method for forming the same. The semiconductor structure includes a first semiconductor chip and N solder bumps in direct physical contact with the first semiconductor chip, wherein N is a positive integer. The semiconductor structure also includes a first solder wall on a perimeter of the first semiconductor chip such that the first solder wall forms a closed loop surrounding the N solder bumps.

Abstract translation: 其形成结构及其方法。 半导体结构包括与第一半导体芯片直接物理接触的第一半导体芯片和N个焊料凸块，其中N是正整数。 半导体结构还包括在第一半导体芯片的周边上的第一焊料壁，使得第一焊料壁形成围绕N个焊料凸点的闭环。

公开(公告)号：US20060223242A1

公开(公告)日：2006-10-05

申请号：US11277398

申请日：2006-03-24

Applicant: Timothy Daubenspeck ,  Christopher Muzzy ,  Paul McLaughlin ,  Judith Wright ,  Jean Wynne ,  Dae Jung

Inventor： Timothy Daubenspeck ,  Christopher Muzzy ,  Paul McLaughlin ,  Judith Wright ,  Jean Wynne ,  Dae Jung

IPC: H01L21/82

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A crack stop void is formed in a low-k dielectric layer between adjacent fuse structures for preventing propagation of cracks between the adjacent fuse structures during a fuse blow operation. The crack stop void is formed simultaneously with the formation of an interconnect structure.

Abstract translation: 在相邻熔丝结构之间的低k电介质层中形成裂纹阻挡空隙，用于在保险丝熔断操作期间防止相邻熔丝结构之间的裂纹传播。 裂缝停止空隙与形成互连结构同时形成。

公开(公告)号：US20060076677A1

公开(公告)日：2006-04-13

申请号：US10964495

申请日：2004-10-12

Applicant: Timothy Daubenspeck ,  Jeffrey Gambino ,  Christopher Muzzy ,  Wolfgang Sauter

Inventor： Timothy Daubenspeck ,  Jeffrey Gambino ,  Christopher Muzzy ,  Wolfgang Sauter

IPC: H01L23/48

CPC classification number: H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/03009 ,  H01L2224/0347 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11906 ,  H01L2224/13006 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01016 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2224/05552

Abstract: A method and system for preventing undercutting of the solder bump in a C4 package by forming a barrier of resist that effectively widens the footprint of the solder bump. The BLM is then etched to the perimeter edge of the barrier rather than the solder bump, thereby precluding any undercutting of the solder bump by the BLM. The barrier may formed by using a half-tone mask that fully exposes the immediately surrounding regions to define a sidewall enclosing the C4 cavity. The barrier may also be formed by applying a second resist prior to, or after, plating the solder and then patterning to inhibit etching directly adjacent to the C4 cavity. The barrier may additionally be formed by overfilling solder into the C4 cavity so that it spreads laterally over the sidewall portion of the resist layer. The resist is then etched anisotropically to leave the barrier. In another embodiment, a taper is introduced into the profile of the C4 cavity by reflowing the resist by an annealing step. The resist is then etched anisotropically to leave the barrier surrounding the C4 solder.

Abstract translation: 一种用于通过形成抗蚀剂屏障来防止C4封装中的焊料凸块的底切的方法和系统，其有效地加宽了焊料凸块的覆盖区。 然后将BLM蚀刻到屏障的周边边缘而不是焊料凸块，从而阻止BLM对焊料凸块的任何底切。 屏障可以通过使用完全暴露紧邻周围区域以限定封闭C4空腔的侧壁的半色调蒙版来形成。 阻挡层也可以通过在电镀之前或之后施加第二抗蚀剂形成，然后形成图案以抑制直接邻近C4腔的蚀刻。 阻挡层可以另外通过将焊料过度填充到C4空腔中形成，使得其在抗蚀剂层的侧壁部分上横向扩展。 然后将抗蚀剂各向异性地蚀刻以离开屏障。 在另一个实施例中，通过退火步骤回流抗蚀剂，将锥形引入到C4空腔的轮廓中。 然后将抗蚀剂各向异性地蚀刻以留下围绕C4焊料的阻挡层。

公开(公告)号：US20070252274A1

公开(公告)日：2007-11-01

申请号：US11380215

申请日：2006-04-26

Applicant: Timothy Daubenspeck ,  Mukta Farooq ,  Jeffrey Gambino ,  Christopher Muzzy ,  Kevin Petrarca ,  Wolfgang Sauter

Inventor： Timothy Daubenspeck ,  Mukta Farooq ,  Jeffrey Gambino ,  Christopher Muzzy ,  Kevin Petrarca ,  Wolfgang Sauter

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L24/03 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/034 ,  H01L2224/03616 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05006 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/05083 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/0517 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05546 ,  H01L2224/05556 ,  H01L2224/05559 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/113 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/01007 ,  H01L2924/00015 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A method for forming preferably Pb-lead C4 connections or capture pads with ball limiting metallization on an integrated circuit chip by using a damascene process and preferably Cu metallization in the chip and in the ball limiting metallization for compatibility. In two one embodiment, the capture pad is formed in the top insulating layer and it also serves as the final level of metallization in the chip.

Abstract translation: 一种用于在集成电路芯片上形成优选Pb-lead C4连接或具有球限制金属化的捕获焊盘的方法，其通过使用镶嵌工艺并且优选地在芯片中的Cu金属化和用于兼容性的球限制金属化中。 在两个实施例中，捕获垫形成在顶部绝缘层中，并且还用作芯片中金属化的最终级别。

公开(公告)号：US20070080455A1

公开(公告)日：2007-04-12

申请号：US11163235

申请日：2005-10-11

Applicant: Donna Zupanski-Nielsen ,  William Landers ,  Ian Melville ,  Roger Quon ,  Timothy Daubenspeck ,  Kamalesh Srivastava ,  Mary Cullinan-Scholl ,  Lawrence Clevenger ,  Christopher Muzzy

Inventor： Donna Zupanski-Nielsen ,  William Landers ,  Ian Melville ,  Roger Quon ,  Timothy Daubenspeck ,  Kamalesh Srivastava ,  Mary Cullinan-Scholl ,  Lawrence Clevenger ,  Christopher Muzzy

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L24/13 ,  H01L21/76831 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/11334 ,  H01L2224/1148 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/00

Abstract: A semiconductor having an insulating layer, a contact pad, a via, and a sacrificial dielectric cap is provided. The contact pad is embedded in the insulating layer, where the contact pad has a top metal layer of copper. The via creates an opening over the top metal layer. The sacrificial dielectric cap is over at least the top metal layer.

Abstract translation: 提供具有绝缘层，接触焊盘，通孔和牺牲电介质盖的半导体。 接触垫嵌入在绝缘层中，其中接触垫具有铜的顶部金属层。 通孔在顶部金属层上形成一个开口。 牺牲绝缘帽至少在顶部金属层之上。

公开(公告)号：US20070013071A1

公开(公告)日：2007-01-18

申请号：US11160461

申请日：2005-06-24

Applicant: James Adkisson ,  Timothy Daubenspeck ,  Jeffrey Gambino ,  Christopher Muzzy ,  Wolfgang Sauter

Inventor： James Adkisson ,  Timothy Daubenspeck ,  Jeffrey Gambino ,  Christopher Muzzy ,  Wolfgang Sauter

IPC: H01L23/52

CPC classification number: H01L24/05 ,  H01L22/32 ,  H01L22/34 ,  H01L24/06 ,  H01L2224/05624 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/00014

Abstract: A structure and a method for forming the same. The structure includes (a) a substrate having a top substrate surface; (b) an integrated circuit on the top substrate surface, wherein the integrated circuit includes a bond pad electrically connected to a transistor of the integrated circuit; (c) a protection ring on the top substrate surface and on a perimeter of the integrated circuit; (c) a kerf region on the top substrate surface, wherein the protection ring is sandwiched between and physically isolates the integrated circuit and the kerf region, wherein the kerf region includes a probe pad electrically connected to the bond pad, and wherein the kerf region is adapted to be destroyed by chip dicing without damaging the integrated circuit and the protection ring.

Abstract translation: 一种结构及其形成方法。 该结构包括（a）具有顶部衬底表面的衬底; （b）在顶部衬底表面上的集成电路，其中所述集成电路包括电连接到所述集成电路的晶体管的接合焊盘; （c）在顶部基板表面上和集成电路的周边上的保护环; （c）顶部衬底表面上的切口区域，其中所述保护环夹在所述集成电路和所述切口区域之间并物理隔离所述集成电路和所述切口区域，其中所述切口区域包括电连接到所述接合焊盘的探针焊盘，并且其中所述切口区域 适用于通过芯片切割而损坏，而不会损坏集成电路和保护环。