公开(公告)号：US5383149A

公开(公告)日：1995-01-17

申请号：US294855

申请日：1994-08-29

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/8246 ,  H01L27/112 ,  G11C17/12

CPC分类号： H01L27/112

摘要： A ROM device provides a double density memory array. The word line array is composed of transversely disposed conductors sandwiched between two arrays of bit lines which are orthogonally disposed relative to the word line array. The two arrays of bit lines are stacked with one above and with one below the word line array. A first gate oxide layer is located between the word line array and a first one of the array of bit lines and a second gate oxide layer is located between the word line array and a the other of the arrays of bit lines. The two parallel sets of polysilicon thin, film transistors are formed with the word lines serving as gates for the transistors.

摘要翻译： ROM设备提供双密度存储器阵列。 字线阵列由夹在相对于字线阵列正交设置的位线阵列之间的横向布置的导体组成。 位线的两个阵列以一个上面堆叠，并且一个在字线阵列下方堆叠。 第一栅极氧化物层位于字线阵列和位线阵列中的第一栅极氧化物层之间，并且第二栅极氧化物层位于字线阵列和位线阵列中的另一个之间。 形成两个并联的多晶硅薄膜晶体管，其中字线用作晶体管的栅极。

公开(公告)号：US5350710A

公开(公告)日：1994-09-27

申请号：US080536

申请日：1993-06-24

申请人： Gary Hong ,  Joe Ko

发明人： Gary Hong ,  Joe Ko

IPC分类号： H01L23/485 ,  H01L23/525 ,  H01L27/02 ,  H01L21/14

CPC分类号： H01L24/05 ,  H01L23/5252 ,  H01L27/0251 ,  H01L2224/05554 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/3011

摘要： A multi-level conductive interconnection for an integrated circuit with an antifuse device is formed, in and on a silicon substrate, wherein there are large contact pad areas at the periphery of the interconnection. The antifuse device is formed from a thin dielectric between a first and second conductor and is connected to the integrated circuit, and is also connected to a ground reference through a silicon junction in the substrate. The large contact pad area is formed with a layer of metal, and is connected to the integrated circuit through the antifuse device, wherein the antifuse device electrically isolates the contact pad and the integrated circuit to prevent charge build-up during subsequent processing. There is further processing in a plasma environment that would normally produce electrical charge build-up at the gate oxide of the integrated circuit, but wherein the antifuse device prevents charge build-up. A voltage is applied to the antifuse device to create a low impedance element, and formation of the integrated circuit is completed.

摘要翻译： 在硅衬底中和硅衬底上形成用于具有反熔丝装置的集成电路的多级导电互连，其中在互连的周边处存在大的接触焊盘区域。 反熔丝装置由第一和第二导体之间的薄电介质形成，并连接到集成电路，并且还通过衬底中的硅结连接到接地基准。 大接触焊盘区域形成有一层金属，并通过反熔丝装置连接到集成电路，其中反熔丝装置电气隔离接触焊盘和集成电路，以防止后续处理期间的电荷积聚。 在等离子体环境中进一步处理通常会在集成电路的栅极氧化层产生电荷积累，但是其中反熔丝装置防止电荷积聚。 向反熔丝装置施加电压以产生低阻抗元件，并且完成集成电路的形成。

公开(公告)号：US5308777A

公开(公告)日：1994-05-03

申请号：US98044

申请日：1993-07-28

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/8246 ,  H01L27/112 ,  H01L21/265

CPC分类号： H01L27/1126 ,  H01L27/112

摘要： A semiconductor device and a method of manufacturing a semiconductor device includes the steps of forming a first conductivity type layer on one surface of a work piece comprising a semiconductor substrate. A gate oxide is formed on the surface of the substrate. A first conductive structure is formed on the gate oxide consisting essentially of polysilicon. An insulating structure is formed in contact with the first conductive structure. Material is removed from the surface of the first conductive structure to expose at least a portion of the surface of the first layer, and to form on the remaining structure on the workpiece a second conductive structure consisting essentially of polysilicon. The polysilicon is in electrical contact with the first conductive structure. Thus, a compound conductive structure is provided on the work piece.

摘要翻译： 半导体器件和半导体器件的制造方法包括以下步骤：在包括半导体衬底的工件的一个表面上形成第一导电类型层。 栅极氧化物形成在衬底的表面上。 在基本上由多晶硅组成的栅极氧化物上形成第一导电结构。 绝缘结构形成为与第一导电结构接触。 从第一导电结构的表面去除材料以暴露第一层的表面的至少一部分，并且在工件上的剩余结构上形成基本上由多晶硅组成的第二导电结构。 多晶硅与第一导电结构电接触。 因此，在工件上设置复合导电结构。

公开(公告)号：US06396745B1

公开(公告)日：2002-05-28

申请号：US09783868

申请日：2001-02-15

申请人： Gary Hong ,  Hwi-Huang Chen ,  Wen-Chi Ting

发明人： Gary Hong ,  Hwi-Huang Chen ,  Wen-Chi Ting

IPC分类号： G11C700

CPC分类号： G11C16/3427 ,  G11C16/0433 ,  H01L29/42324 ,  H01L29/7883

摘要： In present invention we provide a vertical two-transistor memory cell consisted of a MOS transistor and an ETOX cell. One of the drain or source of the MOS transistor is connected to the control gate of the ETOX cell, the other is acted as the control gate of the vertical two-transistor memory cell and is connected to a control line. And the gate of the MOS transistor is acted as the select gate of the vertical two-transistor memory cell and is connected to a word line. The drain of ETOX cell is connected to a bit line, and the source of ETOX cell is grounded. The vertical two-transistor memory cell can be programmed by channel Fowler-Nordheim tunneling of electrons which is injected from the substrate through the channel and tunnel oxide into the floating gate. Such memory cell can avoid the word line disturb by controlling the word line. The memory cell can be also erased by channel Fowler-Nordheim tunneling, in which the electrons is withdrawn from the floating gate through the tunnel oxide and channel to the substrate. In addition, the vertical two-transistor memory cell can be also programmed by conventional methods such as hot electron injection and drain Fowler-Nordheim tunneling, and can be also erased by negative gate source erase or drain Fowler-Nordheim tunneling erase.

摘要翻译： 在本发明中，我们提供了由MOS晶体管和ETOX单元组成的垂直双晶体管存储单元。 MOS晶体管的漏极或源极之一连接到ETOX单元的控制栅极，另一个作为垂直双晶体管存储单元的控制栅极并连接到控制线。 并且MOS晶体管的栅极用作垂直双晶体管存储单元的选择栅极并连接到字线。 ETOX电池的漏极连接到位线，ETOX电池的源极接地。 垂直双晶体管存储单元可以通过通道Fowler-Nordheim隧道进行编程，电子从基板通过沟道注入并将隧道氧化物注入浮栅。 这样的存储单元可以通过控制字线来避免字线干扰。 还可以通过通道Fowler-Nordheim隧道擦除存储单元，其中电子通过隧道氧化物和通道从浮栅取出到衬底。 此外，垂直双晶体管存储单元也可以通过诸如热电子注入和漏极Fowler-Nordheim隧道的常规方法进行编程，并且还可以通过负栅极源擦除或漏极Fowler-Nordheim隧道擦除来擦除。

公开(公告)号：US06235576B1

公开(公告)日：2001-05-22

申请号：US09241522

申请日：1999-02-01

申请人： Gary Hong ,  Anchor Chen

发明人： Gary Hong ,  Anchor Chen

IPC分类号： H01L2120

CPC分类号： H01L28/92 ,  H01L21/76895 ,  H01L27/10852

摘要： A method for manufacturing a cylindrical capacitor on a substrate includes the steps of providing a semiconductor substrate having a first conductive layer thereon, and then forming an insulation layer over the first conductive layer. The insulation layer can be a silicon nitride layer. The insulation layer is patterned to leave a portion of the patterned insulation layer above the node contact region. Thereafter, spacers are formed on the sidewalls of the patterned insulation layer such that the spacers are formed from a material that differs from the insulation layer and the first conductive layer. Next, an etching operation is conducted using the patterned insulation layer and the spacers as a mask to remove a portion of the first conductive layer. After that, the patterned insulation layer is removed. Then, a second etching operation is carried out using the spacers as a mask so that some more material from the upper portion of the first conductive layer is removed. Ultimately, a cylindrical shape structure that serves as the lower electrode of a capacitor is formed. Finally, the spacers are removed, and then a dielectric layer and a second conductive layer are sequentially formed over the cylindrical lower electrode to complete the fabrication of a cylindrical capacitor.

摘要翻译： 一种用于在基板上制造圆柱形电容器的方法包括以下步骤：在其上提供具有第一导电层的半导体衬底，然后在第一导电层上形成绝缘层。 绝缘层可以是氮化硅层。 将绝缘层图案化以将图案化绝缘层的一部分留在节点接触区域上方。 此后，在图案化绝缘层的侧壁上形成间隔物，使得间隔物由与绝缘层和第一导电层不同的材料形成。 接下来，使用图案化绝缘层和间隔物作为掩模进行蚀刻操作以去除第一导电层的一部分。 之后，去除图案化绝缘层。 然后，使用间隔物作为掩模进行第二蚀刻操作，从而去除来自第一导电层的上部的一些更多的材料。 最终，形成用作电容器的下电极的圆柱形结构。 最后，去除间隔物，然后在圆柱形下电极上依次形成电介质层和第二导电层，以完成圆柱形电容器的制造。

公开(公告)号：US06232214B1

公开(公告)日：2001-05-15

申请号：US09316475

申请日：1999-05-21

申请人： Claymens Lee ,  Gary Hong

发明人： Claymens Lee ,  Gary Hong

IPC分类号： H01L214763

CPC分类号： H01L21/7682

摘要： A method for fabricating an inter-metal dielectric layer. Several conducting wires are formed on a substrate, and openings lie between the adjacent conducting wires. A first dielectric layer fills the openings, and the surface of the first dielectric layer is lower than that of the conducting wires. A spacer is formed on a sidewall of each of the conducting wires. The first dielectric layer is removed to expose the bottom of the spacer. A second dielectric layer is formed to cover the conducting wires.

摘要翻译： 一种制造金属间介电层的方法。 在基板上形成几根导线，开口位于相邻的导线之间。 第一电介质层填充开口，并且第一电介质层的表面低于导线的表面。 在每个导线的侧壁上形成间隔物。 去除第一介电层以露出间隔物的底部。 形成第二电介质层以覆盖导线。

公开(公告)号：US06215147B1

公开(公告)日：2001-04-10

申请号：US09235261

申请日：1999-01-22

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A flash memory structure and a method of fabricating the same are provided. The flash memory structure is formed with buried bit lines that are lower in resistance, are shallower in buried depth into the substrate, and have a larger punchthrough margin than the prior art. The flash memory structure is constructed on a semiconductor substrate. A tunneling oxide layer is formed over the substrate. A plurality of floating gates is formed at predefined locations over the tunneling oxide layer. A plurality of sidewall spacers is formed on the sidewalls of the floating gates. A plurality of selective polysilicon blocks is formed over the substrate, each being formed between one neighboring pair of the floating gates. An ion-implantation process is performed to dope an impurity element through these selective polysilicon blocks into the substrate to thereby form a plurality of impurity-doped regions in the substrate to serve as a plurality of buried bit line for the flash memory device. A plurality of insulating layers is formed respectively over the selective polysilicon blocks. A dielectric layer is formed to cover all of the floating gates and the insulating layers, and finally, a plurality of control gates are formed over the dielectric layer, each being located above one of the floating gates.

摘要翻译： 提供闪存结构及其制造方法。 闪速存储器结构形成有电阻较低的掩埋位线，埋入深度较浅的衬底中，并且具有比现有技术更大的穿通余量。 闪存结构构造在半导体衬底上。 在衬底上形成隧道氧化物层。 在隧道氧化物层上的预定位置处形成多个浮动栅极。 多个侧壁间隔件形成在浮动栅极的侧壁上。 在衬底上形成多个选择性多晶硅块，每个选择性多晶硅块形成在一对相邻的浮置栅极之间。 执行离子注入工艺以将杂质元素通过这些选择性多晶硅块掺杂到衬底中，从而在衬底中形成多个杂质掺杂区域，以用作闪存器件的多个掩埋位线。 分别在选择性多晶硅块上形成多个绝缘层。 形成介电层以覆盖所有浮动栅极和绝缘层，最后，在电介质层上形成多个控制栅极，每个控制栅极位于浮动栅极之一上方。

公开(公告)号：US6037234A

公开(公告)日：2000-03-14

申请号：US23879

申请日：1998-02-13

申请人： Gary Hong ,  Anchor Chen

发明人： Gary Hong ,  Anchor Chen

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L21/20 ,  H01L21/28 ,  H01L21/44

CPC分类号： H01L27/10852 ,  H01L28/91 ,  H01L21/76807

摘要： A method of fabricating a capacitor in a DRAM. A semiconductor substrate having a metal-oxide-semiconductor is provided. Using only one photolithography process, a bottom electrode is formed. By forming a dielectric layer over the substrate, and a poly-silicon layer on the dielectric layer, a capacitor is formed.

摘要翻译： 一种在DRAM中制造电容器的方法。 提供具有金属氧化物半导体的半导体衬底。 仅使用一个光刻工艺，形成底部电极。 通过在基板上形成电介质层，在电介质层上形成多晶硅层，形成电容器。

公开(公告)号：US5994745A

公开(公告)日：1999-11-30

申请号：US428766

申请日：1995-04-24

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/8246 ,  H01L27/11

CPC分类号： H01L27/1126 ,  Y10S257/903

摘要： A process of fabricating a mask type ROM is described wherein second type impurity ions are implanted into a semiconductor substrate having a first opposite type background impurity to form a depletion region adjacent the surface. A plurality of parallel nitride lines are formed on the surface, and a first gate oxide formed on the spaces between the nitride lines. Subsequently, a first layer of doped polycrystalline silicon is deposited over the nitride lines, and the layer etched back to expose the top surfaces of the nitride lines. After the nitride lines are removed, a thin gate oxide layer is formed on the exposed surface of the substrate, and on the surfaces of the resultant first polycrystalline gate electrode lines. A second layer of doped polycrystalline silicon is deposited over the polycrystalline silicon lines, and it is etched back. The etch back of the first, and also the second polycrystalline silicon layers, produces an elongated central depression in each of the resultant lines. Then a layer of insulating material is deposited over the surface. A photoresist layer is deposited on the surface of the insulating layer exposed, and developed to define the desired code implant pattern.

摘要翻译： 描述了制造掩模型ROM的工艺，其中将第二类型杂质离子注入到具有第一相反类型背景杂质的半导体衬底中，以形成邻近表面的耗尽区。 在表面上形成多个平行的氮化物线，并且在氮化物线之间的空间上形成第一栅极氧化物。 随后，在氮化物线上沉积第一层掺杂多晶硅，并且将该层回蚀刻以暴露氮化物线的顶表面。 在去除氮化物线之后，在衬底的暴露表面上和所得第一多晶栅极电极线的表面上形成薄的栅极氧化物层。 第二层掺杂多晶硅沉积在多晶硅线上，并被回蚀刻。 第一和第二多晶硅层的回蚀在每个所得到的线中产生细长的中心凹陷。 然后在表面上沉积一层绝缘材料。 光刻胶层沉积在暴露于绝缘层的表面上，并显影以确定所需的代码植入模式。

公开(公告)号：US5976977A

公开(公告)日：1999-11-02

申请号：US975494

申请日：1997-11-21

申请人： Gary Hong

发明人： Gary Hong

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A DRAM capacitor is formed using a process that avoids high temperature processing steps and which emphasizes low cost processes. An interlayer dielectric, typically CVD TEOS oxide, is provided over the transfer FET and bit line contact of the DRAM cell. The interlayer dielectric is planarized and an etch stop layer is provided over the planarized surface of the etch stop layer. A contact via is formed to expose a source/drain region for the transfer FET. Doped polysilicon is provided to fill the contact via and to form a first layer of doped polysilicon over the etch stop layer. The first polysilicon layer is patterned to form a plate aligned over the contact via using a first photoresist mask and etching. The first photoresist mask is left in place over the plate and a first layer of selective oxide is deposited over the etch stop layer so that the first selective oxide layer does not deposit over the photoresist mask. The first photoresist mask is then removed to expose the surface of the plate and a second doped polysilicon layer is provided over the first selective oxide layer and in contact with the first polysilicon plate. A second photoresist mask is provided over the second polysilicon layer and the second polysilicon layer is etched to define fins extending upward and outward from the first polysilicon plate. This process is repeated to form as complex of a structure for the lower capacitor electrode as is desired.

摘要翻译： 使用避免高温处理步骤并且强调低成本处理的过程形成DRAM电容器。 在DRAM单元的转移FET和位线接触之上提供层间电介质，通常为CVD TEOS氧化物。 层间电介质被平坦化，并且蚀刻停止层设置在蚀刻停止层的平坦化表面之上。 形成接触通孔以暴露转移FET的源极/漏极区域。 提供掺杂多晶硅以填充接触通孔并在蚀刻停止层上形成第一掺杂多晶硅层。 图案化第一多晶硅层以形成通过第一光致抗蚀剂掩模和蚀刻在接触通孔上对齐的板。 将第一光致抗蚀剂掩模留在板上的适当位置，并且在蚀刻停止层上沉积第一选择性氧化物层，使得第一选择性氧化物层不沉积在光致抗蚀剂掩模上。 然后去除第一光致抗蚀剂掩模以暴露板的表面，并且在第一选择性氧化物层上提供第二掺杂多晶硅层并与第一多晶硅板接触。 在第二多晶硅层上提供第二光致抗蚀剂掩模，并且蚀刻第二多晶硅层以限定从第一多晶硅板向上和向外延伸的翅片。 重复该过程以形成如下所需的用于下电容器电极的结构的复合物。