公开(公告)号：US08592293B2

公开(公告)日：2013-11-26

申请号：US13028673

申请日：2011-02-16

申请人： Jeffrey B. Johnson ,  Xuefeng Liu ,  Bradley A. Orner ,  Robert M. Rassel

发明人： Jeffrey B. Johnson ,  Xuefeng Liu ,  Bradley A. Orner ,  Robert M. Rassel

IPC分类号： H01L21/28

CPC分类号： H01L29/872 ,  H01L21/8249 ,  H01L27/0635 ,  H01L27/0814 ,  H01L29/161 ,  H01L29/47 ,  H01L29/66143

摘要： A method for forming a Schottky barrier diode on a SiGe BiCMOS wafer, including forming a structure which provides a cutoff frequency (Fc) above about 1.0 THz. In embodiments, the structure which provides a cutoff frequency (Fc) above about 1.0 THz may include an anode having an anode area which provides a cutoff frequency (FC) above about 1.0 THz, an n-epitaxial layer having a thickness which provides a cutoff frequency (FC) above about 1.0 THz, a p-type guardring at an energy and dosage which provides a cutoff frequency (FC) above about 1.0 THz, the p-type guardring having a dimension which provides a cutoff frequency (FC) above about 1.0 THz, and a well tailor with an n-type dopant which provides a cutoff frequency (FC) above about 1.0 THz.

摘要翻译： 一种在SiGe BiCMOS晶片上形成肖特基势垒二极管的方法，包括形成提供高于约1.0THz的截止频率（Fc）的结构。 在实施例中，提供高于约1.0THz的截止频率（Fc）的结构可以包括具有提供高于约1.0THz的截止频率（FC）的阳极区域的阳极，具有提供截止频率 频率（FC）高于约1.0THz，在提供高于约1.0THz的截止频率（FC）的能量和剂量下的p型防护，所述p型护罩具有提供高于约截止频率（FC）的尺寸 1.0 THz，以及具有n型掺杂剂的良好裁缝，其提供高于约1.0THz的截止频率（FC）。

公开(公告)号：US20130187198A1

公开(公告)日：2013-07-25

申请号：US13358180

申请日：2012-01-25

申请人： Renata Camillo-Castillo ,  Zhong-Xiang He ,  Jeffrey B. Johnson ,  Qizhi Liu ,  Xuefeng Liu

发明人： Renata Camillo-Castillo ,  Zhong-Xiang He ,  Jeffrey B. Johnson ,  Qizhi Liu ,  Xuefeng Liu

IPC分类号： H01L29/737 ,  G06F17/50 ,  H01L21/331

CPC分类号： H01L29/417 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/7371

摘要： A heterojunction bipolar transistor (HBT) structure, method of manufacturing the same and design structure thereof are provided. The HBT structure includes a semiconductor substrate having a sub-collector region therein. The HBT structure further includes a collector region overlying a portion of the sub-collector region. The HBT structure further includes an intrinsic base layer overlying at least a portion of the collector region. The HBT structure further includes an extrinsic base layer adjacent to and electrically connected to the intrinsic base layer. The HBT structure further includes an isolation region extending vertically between the extrinsic base layer and the sub-collector region. The HBT structure further includes an emitter overlying a portion of the intrinsic base layer. The HBT structure further includes a collector contact electrically connected to the sub-collector region. The collector contact advantageously extends through at least a portion of the extrinsic base layer.

摘要翻译： 提供异质结双极晶体管（HBT）结构，其制造方法及其设计结构。 HBT结构包括其中具有亚集电极区域的半导体衬底。 HBT结构还包括覆盖子集电极区域的一部分的集电极区域。 HBT结构还包括覆盖集电极区域的至少一部分的本征基极层。 HBT结构还包括与本征基极层相邻并电连接的外部基极层。 HBT结构还包括在外部基极层和副集电极区之间垂直延伸的隔离区。 HBT结构还包括覆盖本征基极层的一部分的发射极。 HBT结构还包括电连接到子集电极区的集电极触点。 收集器触点有利地延伸穿过外部基极层的至少一部分。

公开(公告)号：US08492843B2

公开(公告)日：2013-07-23

申请号：US13449419

申请日：2012-04-18

申请人： Jeffrey B. Johnson ,  Alvin J. Joseph ,  Robert M. Rassel ,  Yun Shi

发明人： Jeffrey B. Johnson ,  Alvin J. Joseph ,  Robert M. Rassel ,  Yun Shi

IPC分类号： H01L29/786

CPC分类号： H01L29/93 ,  H01L29/7391

摘要： A varactor diode includes a portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate and a gate electrode located thereupon. A first electrode having a doping of a first conductivity type laterally abuts a doped semiconductor region having the first conductivity type, which laterally abuts a second electrode having a doping of a second conductivity type, which is the opposite of the first conductivity type. A hyperabrupt junction is formed between the second doped semiconductor region and the second electrode. The gate electrode controls the depletion of the first and second doped semiconductor regions, thereby varying the capacitance of the varactor diode. A design structure for the varactor diode is also provided.

摘要翻译： 变容二极管包括绝缘体上半导体（SOI）衬底的顶部半导体层的一部分和位于其上的栅电极。 具有第一导电类型的掺杂的第一电极横向邻接具有第一导电类型的掺杂半导体区域，其横向邻接具有与第一导电类型相反的第二导电类型的掺杂的第二电极。 在第二掺杂半导体区域和第二电极之间形成超破坏结。 栅电极控制第一和第二掺杂半导体区的耗尽，从而改变变容二极管的电容。 还提供了变容二极管的设计结构。

公开(公告)号：US20120181628A1

公开(公告)日：2012-07-19

申请号：US13430018

申请日：2012-03-26

申请人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Jeffrey B. Johnson ,  Chung H. Lam ,  Beth A. Rainey ,  Michael J. Zierak

发明人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Jeffrey B. Johnson ,  Chung H. Lam ,  Beth A. Rainey ,  Michael J. Zierak

IPC分类号： H01L29/78

CPC分类号： H01L29/66477 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7834 ,  H01L29/792

摘要： A prompt-shift device having reduced programming time in the sub-millisecond range is provided. The prompt-shift device includes an altered extension region located within said semiconductor substrate and on at least one side of the patterned gate region, and an altered halo region located within the semiconductor substrate and on at least one side of the patterned gate region. The altered extension region has an extension ion dopant concentration of less than about 1E20 atoms/cm3, and the altered extension region has a halo ion dopant concentration of greater than about 5E18 atoms/cm3. The altered halo region is in direct contact with the altered extension region.

摘要翻译： 提供了在亚毫秒范围内减少编程时间的提示移位装置。 快速移位装置包括位于所述半导体衬底内并且在图案化栅极区域的至少一侧上的改变的扩展区域，以及位于半导体衬底内以及位于图案化栅极区域的至少一侧的改变的卤素区域。 改变的延伸区域具有小于约1E20原子/ cm3的延伸离子掺杂剂浓度，并且改变的延伸区域具有大于约5E18原子/ cm3的卤素离子掺杂剂浓度。 改变的晕区与改变的延伸区直接接触。

公开(公告)号：US20120112280A1

公开(公告)日：2012-05-10

申请号：US12943084

申请日：2010-11-10

申请人： Jeffrey B. Johnson ,  Shreesh Narasimha ,  Hasan M. Nayfeh ,  Viorel Ontalus ,  Robert R. Robison

发明人： Jeffrey B. Johnson ,  Shreesh Narasimha ,  Hasan M. Nayfeh ,  Viorel Ontalus ,  Robert R. Robison

IPC分类号： H01L29/06 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7824 ,  H01L21/76237 ,  H01L21/84 ,  H01L27/1203

摘要： A structure, a FET, a method of making the structure and of making the FET. The structure including: a silicon layer on a buried oxide (BOX) layer of a silicon-on-insulator substrate; a trench in the silicon layer extending from a top surface of the silicon layer into the silicon layer, the trench not extending to the BOX layer, a doped region in the silicon layer between and abutting the BOX layer and a bottom of the trench, the first doped region doped to a first dopant concentration; a first epitaxial layer, doped to a second dopant concentration, in a bottom of the trench; a second epitaxial layer, doped to a third dopant concentration, on the first epitaxial layer in the trench; and wherein the third dopant concentration is greater than the first and second dopant concentrations and the first dopant concentration is greater than the second dopant concentration.

摘要翻译： 一种结构，一种FET，一种制造该结构和制造该FET的方法。 该结构包括：绝缘体上硅衬底上的掩埋氧化物（BOX）层上的硅层; 所述硅层中的沟槽从所述硅层的顶表面延伸到所述硅层中，所述沟槽不延伸到所述BOX层，所述硅层中的掺杂区域在所述BOX层之间并与所述沟槽的底部邻接， 掺杂到第一掺杂剂浓度的第一掺杂区; 在沟槽的底部掺杂到第二掺杂剂浓度的第一外延层; 在沟槽中的第一外延层上掺杂到第三掺杂剂浓度的第二外延层; 并且其中所述第三掺杂剂浓度大于所述第一和第二掺杂剂浓度，并且所述第一掺杂剂浓度大于所述第二掺杂剂浓度。

公开(公告)号：US20120086077A1

公开(公告)日：2012-04-12

申请号：US12899635

申请日：2010-10-07

申请人： DAVID M FRIED ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Gan Wang ,  Geng Wang ,  Yanli Zhang

发明人： DAVID M FRIED ,  Jeffrey B. Johnson ,  Kevin McStay ,  Paul C. Parries ,  Chengwen Pei ,  Gan Wang ,  Geng Wang ,  Yanli Zhang

IPC分类号： H01L29/06 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L27/1203 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7833

摘要： An FET structure on a semiconductor substrate which includes forming recesses for a source and a drain of the gate structure on a semiconductor substrate, halo implanting regions through the bottom of the source and drain recesses, the halo implanted regions being underneath the gate stack, implanting junction butting at the bottom of the source and drain recesses, and filling the source and drain recesses with a doped epitaxial material. In exemplary embodiments, the semiconductor substrate is a semiconductor on insulator substrate including a semiconductor layer on a buried oxide layer. In exemplary embodiments, the junction butting and halo implanted regions are in contact with the buried oxide layer. In other exemplary embodiments, there is no junction butting. In exemplary embodiments, halo implants implanted to a lower part of the FET body underneath the gate structure provide higher doping level in lower part of the FET body to reduce body resistance, without interfering with FET threshold voltage.

摘要翻译： 半导体衬底上的FET结构，其包括在半导体衬底上形成用于栅极结构的源极和漏极的凹槽，通过源极和漏极凹部的底部的晕圈注入区域，位于栅极叠层下方的晕圈注入区域，注入 在源极和漏极凹部的底部接合，并且用掺杂的外延材料填充源极和漏极凹部。 在示例性实施例中，半导体衬底是在掩埋氧化物层上包括半导体层的绝缘体上半导体衬底。 在示例性实施例中，接合对接和晕圈注入区域与掩埋氧化物层接触。 在其他示例性实施例中，没有接合对接。 在示例性实施例中，注入到栅极结构下面的FET体的下部的卤素注入在FET体的下部提供更高的掺杂水平，以降低体电阻，而不会干扰FET阈值电压。

公开(公告)号：US07989302B2

公开(公告)日：2011-08-02

申请号：US12795108

申请日：2010-06-07

申请人： Jeffrey B. Johnson ,  Alvin J. Joseph ,  Robert M. Rassel ,  Yun Shi

发明人： Jeffrey B. Johnson ,  Alvin J. Joseph ,  Robert M. Rassel ,  Yun Shi

IPC分类号： H01L21/20

CPC分类号： H01L29/93

摘要： Methods of forming hyper-abrupt p-n junctions and design structures for an integrated circuit containing devices structures with hyper-abrupt p-n junctions. The hyper-abrupt p-n junction is defined in a SOI substrate by implanting a portion of a device layer to have one conductivity type and then implanting a portion of this doped region to have an opposite conductivity type. The counterdoping defines the hyper-abrupt p-n junction. A gate structure carried on a top surface of the device layer operates as a hard mask during the ion implantations to assist in defining a lateral boundary for the hyper-abrupt p-n junction.

摘要翻译： 形成超突变p-n结的方法和包含具有超突变p-n结的器件结构的集成电路的设计结构。 通过将器件层的一部分注入具有一种导电类型，然后将该掺杂区域的一部分注入具有相反的导电型，在SOI衬底中限定超突变p-n结。 反渗透定义了超突变p-n结。 在离子注入期间，在器件层的顶表面上承载的栅结构作为硬掩模进行操作，以有助于限定超突变p-n结的横向边界。

公开(公告)号：US07936041B2

公开(公告)日：2011-05-03

申请号：US11853973

申请日：2007-09-12

申请人： Jeffrey B. Johnson ,  Xuefeng Liu ,  Bradley A. Orner ,  Robert M. Rassel

发明人： Jeffrey B. Johnson ,  Xuefeng Liu ,  Bradley A. Orner ,  Robert M. Rassel

IPC分类号： H01L29/872 ,  H01L21/329

CPC分类号： H01L29/872 ,  H01L21/8249 ,  H01L27/0635 ,  H01L27/0814 ,  H01L29/161 ,  H01L29/47 ,  H01L29/66143

摘要： The structure for millimeter-wave frequency applications, includes a Schottky barrier diode (SBD) with a cutoff frequency (FC) above 1.0 THz formed on a SiGe BiCMOS wafer. A method is also contemplated for forming a Schottky barrier diode on a SiGe BiCMOS wafer, including forming a structure which provides a cutoff frequency (Fc) above about 1.0 THz. In embodiments, the structure which provides a cutoff frequency (Fc) above about 1.0 THz may include an anode having an anode area which provides a cutoff frequency (FC) above about 1.0 THz, an n-epitaxial layer having a thickness which provides a cutoff frequency (FC) above about 1.0 THz, a p-type guardring at an energy and dosage which provides a cutoff frequency (FC) above about 1.0 THz, the p-type guardring having a dimension which provides a cutoff frequency (FC) above about 1.0 THz, and a well tailor with an n-type dopant which provides a cutoff frequency (FC) above about 1.0 THz.

摘要翻译： 毫米波频率应用的结构包括在SiGe BiCMOS晶片上形成的截止频率（FC）大于1.0THz的肖特基势垒二极管（SBD）。 还考虑了在SiGe BiCMOS晶片上形成肖特基势垒二极管的方法，包括形成提供高于约1.0THz的截止频率（Fc）的结构。 在实施例中，提供高于约1.0THz的截止频率（Fc）的结构可以包括具有提供高于约1.0THz的截止频率（FC）的阳极区域的阳极，具有提供截止频率 频率（FC）高于约1.0THz，在提供高于约1.0THz的截止频率（FC）的能量和剂量下的p型防护，所述p型护罩具有提供高于约截止频率（FC）的尺寸 1.0 THz，以及具有n型掺杂剂的良好裁缝，其提供高于约1.0THz的截止频率（FC）。

公开(公告)号：US07932155B2

公开(公告)日：2011-04-26

申请号：US11760288

申请日：2007-06-08

申请人： James S. Dunn ,  David L. Harame ,  Jeffrey B. Johnson ,  Alvin J. Joseph

发明人： James S. Dunn ,  David L. Harame ,  Jeffrey B. Johnson ,  Alvin J. Joseph

IPC分类号： H01L21/8222

CPC分类号： H01L29/7371 ,  H01L27/0823 ,  H01L29/66242

摘要： A method of forming a semiconductor device having two different strains therein is provided. The method includes forming a strain in a first region with a first straining film, and forming a second strain in a second region with a second straining film. Either of the first or second strains may be either tensile or compressive. Additionally the strains may be formed at right angles to one another and may be additionally formed in the same region. In particular a vertical tensile strain may be formed in a base and collector region of an NPN bipolar transistor and a horizontal compressive strain may be formed in the extrinsic base region of the NPN bipolar transistor. A PNP bipolar transistor may be formed with a compression strain in the base and collector region in the vertical direction and a tensile strain in the extrinsic base region in the horizontal direction.

摘要翻译： 提供了形成其中具有两个不同应变的半导体器件的方法。 该方法包括在具有第一应变膜的第一区域中形成应变，并且在第二区域中用第二应变膜形成第二应变。 第一或第二应变中的任一种可以是拉伸的或压缩的。 此外，菌株可以彼此成直角形成，并且可以另外形成在相同的区域中。 特别地，可以在NPN双极晶体管的基极和集电极区域中形成垂直拉伸应变，并且可以在NPN双极晶体管的非本征基极区域中形成水平压缩应变。 PNP双极晶体管可以在垂直方向的基极和集电极区域中形成压缩应变，并且在水平方向上在外部基极区域中形成拉伸应变。

公开(公告)号：US20090294850A1

公开(公告)日：2009-12-03

申请号：US12130460

申请日：2008-05-30

申请人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Jeffrey B. Johnson ,  Chung H. Lam ,  Beth A. Rainey ,  Michael J. Zierak

发明人： Matthew J. Breitwisch ,  Roger W. Cheek ,  Jeffrey B. Johnson ,  Chung H. Lam ,  Beth A. Rainey ,  Michael J. Zierak

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66477 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7834 ,  H01L29/792

摘要： The invention provides a method to enhance the programmability of a prompt-shift device, which reduces the programming time to sub-millisecond times, by altering the extension and halo implants, instead of simply omitting the same from one side of the device as is the case in the prior art prompt-shift devices. The invention includes an embodiment in which no additional masks are employed, or one additional mask is employed. The altered extension implant is performed at a reduced ion dose as compared to a conventional extension implant process, while the altered halo implant is performed at a higher ion dose than a conventional halo implant. The altered halo/extension implant shifts the peak of the electrical field to under an extension dielectric spacer.

摘要翻译： 本发明提供了一种通过改变扩展和光晕注入来提高快速移位设备的可编程性的方法，其将编程时间缩短到几毫秒，而不是从设备的一侧简单地省略它 现有技术中的瞬时移位装置。 本发明包括其中不使用附加掩模的实施例，或者采用一个附加掩模。 与常规的延伸植入过程相比，改变的延伸植入物以降低的离子剂量进行，而改变的晕轮植入物以比常规的晕轮植入物更高的离子剂量进行。 改变的光晕/延伸注入将电场的峰值移动到延伸电介质间隔物下方。