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    Isolated FinFET P-channel/N-channel transistor pair
    82.
    发明授权
    Isolated FinFET P-channel/N-channel transistor pair 有权
    隔离型FinFET P沟道/ N沟道晶体管对

    公开(公告)号：US06974983B1

    公开(公告)日：2005-12-13

    申请号：US10768660

    申请日：2004-02-02

    Applicant: Wiley Eugene Hill ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

    Inventor： Wiley Eugene Hill ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

    IPC: H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L21/062

    CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

    Abstract: A semiconductor device includes an N-channel device and a P-channel device. The N-channel device includes a first source region, a first drain region, a first fin structure, and a gate. The P-channel device includes a second source region, a second drain region, a second fin structure, and the gate. The second source region, the second drain region, and the second fin structure are separated from the first source region, the first drain region, and the first fin structure by a channel stop layer.

    Abstract translation: 半导体器件包括N沟道器件和P沟道器件。 N沟道器件包括第一源极区，第一漏极区，第一鳍结构和栅极。 P沟道器件包括第二源极区，第二漏极区，第二鳍结构和栅极。 第二源极区域，第二漏极区域和第二鳍状结构通过沟道阻挡层与第一源极区域，第一漏极区域和第一鳍片结构分离。

    Strained silicon MOSFET having reduced leakage and method of its formation
    85.
    发明授权
    Strained silicon MOSFET having reduced leakage and method of its formation 有权
    应变硅MOSFET具有减少的泄漏和其形成方法

    公开(公告)号：US06924182B1

    公开(公告)日：2005-08-02

    申请号：US10642375

    申请日：2003-08-15

    Applicant: Qi Xiang ,  Ming Ren Lin ,  Minh V. Ngo ,  Eric N. Paton ,  Haihong Wang

    Inventor： Qi Xiang ,  Ming Ren Lin ,  Minh V. Ngo ,  Eric N. Paton ,  Haihong Wang

    IPC: H01L21/762 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/76

    CPC classification number: H01L21/823878 ,  H01L21/76237 ,  H01L21/823807

    Abstract: The formation of shallow trench isolations in a strained silicon MOSFET includes performing ion implantation in the strained silicon layer in the regions to be etched to form the trenches of the shallow trench isolations. The dosage of the implanted ions and the energy of implantation are chosen so as to damage the crystal lattice of the strained silicon throughout the thickness of the strained silicon layer in the shallow trench isolation regions to such a degree that the etch rate of the strained silicon in those regions is increased to approximately the same as or greater than the etch rate of the underlying undamaged silicon germanium. Subsequent etching yields trenches with significantly reduced or eliminated undercutting of the silicon germanium relative to the strained silicon. This in turn substantially prevents the formation of fully depleted silicon on insulator regions under the ends of the gate, thus improving the MOSFET leakage current.

    Abstract translation: 应变硅MOSFET中的浅沟槽隔离的形成包括在被蚀刻的区域中的应变硅层中执行离子注入以形成浅沟槽隔离的沟槽。 选择注入离子的剂量和注入能量，以便在浅沟槽隔离区域中的应变硅层的整个厚度上损坏应变硅的晶格，使得应变硅的蚀刻速率 在这些区域中增加到大致等于或大于底层未损坏的硅锗的蚀刻速率。 随后的蚀刻产生相对于应变硅显着减少或消除硅锗底切的沟槽。 这又大大防止了在栅极端部的绝缘体区域上形成完全耗尽的硅，从而改善MOSFET漏电流。

    Merged FinFET P-channel/N-channel pair
    86.
    发明授权
    Merged FinFET P-channel/N-channel pair 有权
    合并FinFET P沟道/ N沟道对

    公开(公告)号：US06914277B1

    公开(公告)日：2005-07-05

    申请号：US10674400

    申请日：2003-10-01

    Applicant: Wiley Eugene Hill ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

    Inventor： Wiley Eugene Hill ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

    IPC: H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/76

    CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

    Abstract: A semiconductor device includes an N-channel device and a P-channel device. The N-channel device includes a first source region, a first drain region, a first fin structure, and a gate. The P-channel device includes a second source region, a second drain region, a second fin structure, and the gate. The second source region, the second drain region, and the second fin structure are separated from the first source region, the first drain region, and the first fin structure by an insulating layer.

    Abstract translation: 半导体器件包括N沟道器件和P沟道器件。 N沟道器件包括第一源极区，第一漏极区，第一鳍结构和栅极。 P沟道器件包括第二源极区，第二漏极区，第二鳍结构和栅极。 第二源极区域，第二漏极区域和第二鳍状结构通过绝缘层与第一源极区域，第一漏极区域和第一鳍片结构分离。

    Offset spacer process for forming N-type transistors
    87.
    发明授权
    Offset spacer process for forming N-type transistors 有权
    用于形成N型晶体管的偏置间隔工艺

    公开(公告)号：US06905923B1

    公开(公告)日：2005-06-14

    申请号：US10619877

    申请日：2003-07-15

    Applicant: Eric N. Paton ,  Haihong Wang ,  Qi Xiang

    Inventor： Eric N. Paton ,  Haihong Wang ,  Qi Xiang

    IPC: H01L21/8238

    CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L21/823864

    Abstract: A method of fabricating an SMOS integrated circuit with source and drain junctions utilizes an offset gate spacer for N-type transistors. Ions are implanted to form the source and drain regions in a strained layer. The offset spacer reduces problems associated with Arsenic (As) diffusion on strained semiconductor layers. The process can be utilized for SMOS metal oxide semiconductor field effect transistors (MOSFETs). The strained layer can be a strained silicon layer formed above a germanium layer.

    Abstract translation: 制造具有源极和漏极结的SMOS集成电路的方法利用用于N型晶体管的偏移栅极间隔物。 植入离子以形成应变层中的源区和漏区。 偏移间隔物减少了在应变半导体层上与砷（As）扩散相关的问题。 该工艺可用于SMOS金属氧化物半导体场效应晶体管（MOSFET）。 应变层可以是形成在锗层之上的应变硅层。

    Method of forming strained silicon MOSFET having improved threshold voltage under the gate ends
    88.
    发明授权
    Method of forming strained silicon MOSFET having improved threshold voltage under the gate ends 有权
    形成栅极末端具有改善的阈值电压的应变硅MOSFET的方法

    公开(公告)号：US06893929B1

    公开(公告)日：2005-05-17

    申请号：US10641548

    申请日：2003-08-15

    Applicant: Qi Xiang ,  Ming Ren Lin ,  Minh V. Ngo ,  Haihong Wang

    Inventor： Qi Xiang ,  Ming Ren Lin ,  Minh V. Ngo ,  Haihong Wang

    IPC: H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/10

    CPC classification number: H01L29/6659 ,  H01L21/76237 ,  H01L21/823412 ,  H01L21/823481 ,  H01L29/1054 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7842 ,  Y10S438/933

    Abstract: The formation of shallow trench isolations in a strained silicon MOSFET includes implantation of a dopant into overhang portions of the strained silicon layer and silicon germanium layer at the edges of trenches in which shallow trench isolations are to be formed. The conductivity type of the dopant is chosen to be opposite the conductivity type of the source and drain dopants. The implanted dopant increases the threshold voltage Vt beneath the ends of the gate in overhang portions of the strained silicon layer so that it is approximately equal to or greater than that of the remainder of the MOSFET. The resulting strained silicon MOSFET exhibits reduced leakage current beneath the ends of the gate.

    Abstract translation: 应变硅MOSFET中浅沟槽隔离的形成包括将掺杂剂注入到将要形成浅沟槽隔离的沟槽边缘处的应变硅层和硅锗层的伸出部分。 选择掺杂剂的导电类型与源极和漏极掺杂剂的导电类型相反。 注入的掺杂剂在应变硅层的突出部分中增加栅极端部之下的阈值电压Vt，使得其大致等于或大于MOSFET的其余部分的阈值电压。 所产生的应变硅MOSFET在栅极端部下方表现出减小的漏电流。

    VARYING CARRIER MOBILITY IN SEMICONDUCTOR DEVICES TO ACHIEVE OVERALL DESIGN GOALS
    90.
    发明申请
    VARYING CARRIER MOBILITY IN SEMICONDUCTOR DEVICES TO ACHIEVE OVERALL DESIGN GOALS 有权
    半导体设备的变化载体移动实现总体设计目标

    公开(公告)号：US20050029603A1

    公开(公告)日：2005-02-10

    申请号：US10633504

    申请日：2003-08-05

    Applicant: Bin Yu ,  Shibly Ahmed ,  Haihong Wang

    Inventor： Bin Yu ,  Shibly Ahmed ,  Haihong Wang

    IPC: H01L21/336 ,  H01L27/12 ,  H01L29/786 ,  H01L29/76

    CPC classification number: H01L29/785 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66795

    Abstract: A semiconductor device may include a substrate and an insulating layer formed on the substrate. A first device may be formed on the insulating layer, including a first fin. The first fin may be formed on the insulating layer and may have a first fin aspect ratio. A second device may be formed on the insulating layer, including a second fin. The second fin may be formed on the insulating layer and may have a second fin aspect ratio different from the first fin aspect ratio.

    Abstract translation: 半导体器件可以包括衬底和形成在衬底上的绝缘层。 第一器件可以形成在绝缘层上，包括第一鳍片。 第一翅片可以形成在绝缘层上，并且可以具有第一翅片长宽比。 第二装置可以形成在绝缘层上，包括第二鳍片。 第二翅片可以形成在绝缘层上，并且可以具有与第一翅片长宽比不同的第二翅片长宽比。

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