公开(公告)号：US07019923B2

公开(公告)日：2006-03-28

申请号：US10420236

申请日：2003-04-22

申请人： John D. Leighton ,  Hao Fang ,  Michael J. O'Brien ,  Scott O'Brien ,  Cameron C. Rabe

发明人： John D. Leighton ,  Hao Fang ,  Michael J. O'Brien ,  Scott O'Brien ,  Cameron C. Rabe

IPC分类号： G11B5/09

CPC分类号： H03F3/45085

摘要： A pre-amplifier, a Thevenin writer and a disk drive employing transistors having a breakdown voltage below a circuitry operating voltage. In one embodiment, the pre-amplifier includes an emitter-follower transistor pair couplable to a power supply and a differential transistor pair, having a collector-emitter breakdown voltage below a voltage of the power supply, that receives current from, and controlled by, the emitter-follower transistor pair.

摘要翻译： 前置放大器，戴维南写入器和采用具有低于电路工作电压的击穿电压的晶体管的磁盘驱动器。 在一个实施例中，前置放大器包括可耦合到电源和差分晶体管对的发射极 - 跟随器晶体管对，其具有低于电源电压的集电极 - 发射极击穿电压，其接收来自并由其控制的电流， 射极跟随器晶体管对。

公开(公告)号：US20050072999A1

公开(公告)日：2005-04-07

申请号：US10680665

申请日：2003-10-06

申请人： George Matamis ,  Tuan Pham ,  Henry Chien ,  Hao Fang

发明人： George Matamis ,  Tuan Pham ,  Henry Chien ,  Hao Fang

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A NAND flash memory structure and method of making a flash memory structure with shielding in the bitline direction as well as in wordline and diagonal directions from Yupin effect errors and from distrubs.

摘要翻译： 一种NAND闪速存储器结构和方法，其制造具有在位线方向上的屏蔽的闪存结构以及来自Yupin效应误差和distrubs的字线和对角线方向。

公开(公告)号：US06602776B1

公开(公告)日：2003-08-05

申请号：US10155500

申请日：2002-05-23

申请人： Masaaki Higashitani ,  Hao Fang

发明人： Masaaki Higashitani ,  Hao Fang

IPC分类号： H01L2144

CPC分类号： H01L22/34

摘要： A system and method detecting the presence of polysilicon stringers on a memory array using a polysilicon stringer monitor. The polysilicon stringer monitor includes a continuous type-2 layer of polysilicon forming a first row and a second row across the active region and covering the active region in-between the first and second rows. The polysilicon stringer monitor further includes a continuous type-1 layer of polysilicon extending under the first row, wherein the type-1 layer also covers the active area in-between the first and second rows as well as covers the active area under the second row.

公开(公告)号：US06514830B1

公开(公告)日：2003-02-04

申请号：US10044510

申请日：2002-01-11

申请人： Hao Fang ,  Narbeh Derhacobian

发明人： Hao Fang ,  Narbeh Derhacobian

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L27/11534

摘要： A method of manufacturing a high voltage transistor exhibiting high gated diode breakdown voltage, low leakage and low body effect while avoiding an excessive number of costly masking steps. A high gated diode breakdown voltage is provided in the manufacturing process by masking the high voltage junctions from the conventional field implant and masking the source/drain regions from the conventional threshold adjust implant. Angled openings are formed in the field implant blocking mask so that the field implant at varying distances away from the junctions, thus achieving low leakage and a high gated diode breakdown voltage. The field implant blocking mask is extended over the channel area, thereby producing a transistor with low body effect.

摘要翻译： 一种制造高栅极二极管击穿电压，低泄漏和低体效应的高压晶体管的方法，同时避免过多数量的昂贵的掩蔽步骤。 在制造过程中通过掩蔽来自常规场注入的高压结和从常规阈值调整植入物屏蔽源极/漏极区域来提供高栅极二极管击穿电压。 在场注入阻挡掩模中形成有角度的开口，使得场离子注入距离结点不同的距离，从而实现低泄漏和高门控二极管击穿电压。 场注入阻挡掩模在沟道区域上延伸，从而产生具有低体效应的晶体管。

公开(公告)号：US06472327B2

公开(公告)日：2002-10-29

申请号：US09925205

申请日：2001-08-08

申请人： King Wai Kelwin Ko ,  Mark S. Chang ,  Hao Fang

发明人： King Wai Kelwin Ko ,  Mark S. Chang ,  Hao Fang

IPC分类号： H01L21304

CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L27/11534

摘要： A method and system for etching gate oxide during transistor fabrication is disclosed. The method and system begin by depositing a gate oxide on a substrate, followed by a deposition of a tunnel oxide mask over a portion of the gate oxide. The method and system further include performing a combination dry/wet-etch to remove the gate oxide uncovered by the tunnel oxide mask, which minimizes tunnel oxide undercut.

摘要翻译： 公开了在晶体管制造期间蚀刻栅极氧化物的方法和系统。 该方法和系统首先通过在衬底上沉积栅极氧化物，然后在栅极氧化物的一部分上沉积隧道氧化物掩模。 该方法和系统还包括执行干/湿蚀刻组合以去除未被隧道氧化物掩模覆盖的栅极氧化物，其使隧道氧化物底切最小化。

公开(公告)号：US06376309B2

公开(公告)日：2002-04-23

申请号：US09811288

申请日：2001-03-16

申请人： John JianShi Wang ,  Kent Kuohua Chang ,  Hao Fang ,  Lu You

发明人： John JianShi Wang ,  Kent Kuohua Chang ,  Hao Fang ,  Lu You

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L21/76837 ,  H01L27/115

摘要： The present invention provides a method for reducing the gate aspect ratio of a flash memory device. The method includes forming a tunnel oxide layer on a substrate; forming a polysilicon layer on the tunnel oxide layer; forming an insulating layer on the polysilicon layer; forming a control gate layer on the polysilicon layer; etching at least the tunnel oxide layer, the insulating layer, and the control gate layer to form at least two stack structures; forming a plurality of spacers at sides of the at least two stack structures; and filling at least one gap between the at least two stack structures with an oxide, where the control gate layer provides a gate aspect ratio which allows for a maximum step coverage by the oxide. In a preferred embodiment, the method uses nickel silicide instead of the conventional tungsten silicide in the control gate layers of the cells of the device. Nickel silicide has higher conductivity than conventional silicides, thus a thinner layer of nickel silicide may be used without sacrificing performance. Nickel silicide also has a lower barrier height for holes, thus maintaining a low contact resistance. With a thinner nickel silicide layer, the gate aspect ratio of the cells are lowered, allowing for a maximum step coverage by the gap-filling oxide. The reliability of the device is thus improved.

摘要翻译： 本发明提供一种降低闪速存储器件的栅极纵横比的方法。 该方法包括在衬底上形成隧道氧化物层; 在隧道氧化层上形成多晶硅层; 在所述多晶硅层上形成绝缘层; 在所述多晶硅层上形成控制栅极层; 至少蚀刻隧道氧化物层，绝缘层和控制栅极层以形成至少两个堆叠结构; 在所述至少两个堆叠结构的侧面处形成多个间隔物; 以及用所述氧化物填充所述至少两个堆叠结构之间的至少一个间隙，其中所述控制栅极层提供允许所述氧化物的最大阶跃覆盖的栅极纵横比。 在优选实施例中，该方法在装置的电池的控制栅极层中使用硅化镍代替常规的硅化钨。 硅化镍具有比常规硅化物更高的导电性，因此可以使用更薄的硅化镍层而不牺牲性能。 硅化镍也具有较低的孔的阻挡高度，因此保持低的接触电阻。 利用更薄的硅化镍层，电池的栅极纵横比降低，允许通过间隙填充氧化物的最大阶梯覆盖。 因此提高了装置的可靠性。

公开(公告)号：US06362049B1

公开(公告)日：2002-03-26

申请号：US09435213

申请日：1999-11-05

申请人： Salvatore F. Cagnina ,  Hao Fang ,  John Jianshi Wang ,  Kent Kuohua Chang ,  Masaatzi Higashitani

发明人： Salvatore F. Cagnina ,  Hao Fang ,  John Jianshi Wang ,  Kent Kuohua Chang ,  Masaatzi Higashitani

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L27/11546

摘要： A semiconductor process for fabricating NAND type flash memory devices in a first embodiment includes step which can be performed on a production line which manufactures NOR type flash memory products. A NAND flash memory fabrication process according to a second embodiment simplifies the process and uses fewer masks, thus reducing costs and errors to produce higher yields.

摘要翻译： 在第一实施例中用于制造NAND型闪速存储器件的半导体工艺包括可以在制造NOR型闪存产品的生产线上执行的步骤。 根据第二实施例的NAND闪存制造工艺简化了处理并且使用较少的掩模，从而降低成本和错误以产生更高的产量。

公开(公告)号：US06351017B1

公开(公告)日：2002-02-26

申请号：US09533057

申请日：2000-03-22

申请人： Hao Fang ,  Narbeh Derhacobian

发明人： Hao Fang ,  Narbeh Derhacobian

IPC分类号： H01L31119

CPC分类号： H01L27/11526 ,  H01L27/11534

摘要： A high voltage transistor exhibiting high gated diode breakdown voltage, low leakage and low body effect is formed while avoiding an excessive number of costly masking steps. Embodiments include providing a high gated diode breakdown voltage by masking the high voltage junctions from the conventional field implant and masking the source/drain regions from the conventional threshold adjust implant. Angled openings are formed in the field implant blocking mask so that the field implant at varying distances away from the junctions, thus achieving low leakage and a high gated diode breakdown voltage. The field implant blocking mask is extended over the channel area, thereby producing a transistor with low body effect.

摘要翻译： 形成具有高门控二极管击穿电压，低泄漏和低体效应的高电压晶体管，同时避免过多数量的昂贵的掩蔽步骤。 实施例包括通过掩蔽来自常规场注入的高电压结以及从常规阈值调整植入物屏蔽源/漏区来提供高门控二极管击穿电压。 在场注入阻挡掩模中形成有角度的开口，使得场离子注入距离结点不同的距离，从而实现低泄漏和高门控二极管击穿电压。 场注入阻挡掩模在沟道区域上延伸，从而产生具有低体效应的晶体管。

公开(公告)号：US06228782B1

公开(公告)日：2001-05-08

申请号：US09309994

申请日：1999-05-11

申请人： Hao Fang ,  Massaki Higashitani ,  Narbeh Derhacobian

发明人： Hao Fang ,  Massaki Higashitani ,  Narbeh Derhacobian

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L21/76216 ,  H01L27/115

摘要： Selective high-energy impurity implantation enables optimization of both core and peripheral field isolation without substantially degrading functionality, self-boosting efficiency or otherwise increasing program disturb, thereby improving device performance and reliability. Embodiments include high-energy impurity implantation, after forming core and peripheral field oxide regions in a semiconductor substrate, into the peripheral field oxide region and selected portions of the core field oxide regions corresponding to select transistor areas, while blocking the implant from the core memory cell channel regions. A channel stop implant is performed through the core field oxide regions after etching a first polysilicon layer. The high-energy impurity implant optimizes peripheral field isolation, without degrading self-boosting efficiency, because it is blocked from entering the memory cell channel region. The high-energy implant also enhances isolation in the select transistor areas, thereby preventing an increase in device malfunctions, while the channel stop implant optimizes core field isolation.

摘要翻译： 选择性高能杂质注入使得能够优化核和外围场隔离，而不会显着降低功能性，自增强效率或以其他方式增加程序干扰，从而提高器件性能和可靠性。 实施例包括在半导体衬底中形成核心和外围场氧化物区域之后的高能杂质注入到对应于选择晶体管区域的外围场氧化物区域和核心场氧化物区域的选定部分，同时将核心存储器 细胞通道区。 在蚀刻第一多晶硅层之后，通过核心场氧化物区域进行沟道停止注入。 高能杂质注入优化外围场隔离，而不会降低自增强效率，因为它被阻止进入存储单元通道区。 高能量注入还增强了选择晶体管区域的隔离度，从而防止了器件故障的增加，而通道停止植入则优化了磁芯隔离。

公开(公告)号：US06177345B1

公开(公告)日：2001-01-23

申请号：US09080405

申请日：1998-05-18

申请人： Guarionex Morales ,  Jianshi Wang ,  Judith Q. Rizzuto ,  Hao Fang

发明人： Guarionex Morales ,  Jianshi Wang ,  Judith Q. Rizzuto ,  Hao Fang

IPC分类号： H01L2144

CPC分类号： H01L21/28518 ,  H01L21/32053

摘要： A method of depositing metal silicide onto a semiconductor substrate includes a step of depositing, by a CVD process, a first metal silicide layer with silane gas onto the semiconductor substrate. The method also includes a step of thermally treating and chemically cleaning the semiconductor substrate. The method further includes a step of depositing, by the CVD process, a second metal silicide layer with silane gas onto the semiconductor substrate. By this method, cracks in the metal silicide formed on the semiconductor substrate are minimized.

摘要翻译： 将金属硅化物沉积到半导体衬底上的方法包括通过CVD工艺将具有硅烷气体的第一金属硅化物层沉积到半导体衬底上的步骤。 该方法还包括对半导体衬底进行热处理和化学清洗的步骤。 该方法还包括通过CVD工艺将具有硅烷气体的第二金属硅化物层沉积到半导体衬底上的步骤。 通过这种方法，在半导体衬底上形成的金属硅化物中的裂纹被最小化。