公开(公告)号：US11468329B2

公开(公告)日：2022-10-11

申请号：US17025643

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Suraj Prabhakaran ,  Kshitij A. Doshi ,  Da-Ming Chiang

IPC: G06N3/08 ,  G06N5/04 ,  G06N3/063

Abstract: Examples include techniques to manage training or trained models for deep learning applications. Examples include routing commands to configure a training model to be implemented by a training module or configure a trained model to be implemented by an inference module. The commands routed via out-of-band (OOB) link while training data for the training models or input data for the trained models are routed via inband links.

公开(公告)号：US11451435B2

公开(公告)日：2022-09-20

申请号：US16367626

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Benjamin Graniello ,  Timothy Verrall ,  Andrew J. Herdrich ,  Rashmin Patel ,  Monica Kenguva ,  Brinda Ganesh ,  Alexander Vul ,  Ned M. Smith ,  Suraj Prabhakaran

IPC: H04L41/0803 ,  H04L41/5041

Abstract: Technologies for providing multi-tenant support in edge resources using edge channels include a device that includes circuitry to obtain a message associated with a service provided at the edge of a network. Additionally, the circuitry is to identify an edge channel based on metadata associated with the message. The edge channel has a predefined amount of resource capacity allocated to the edge channel to process the message. Further, the circuitry is to determine the predefined amount of resource capacity allocated to the edge channel and process the message using the allocated resource capacity for the identified edge channel.

公开(公告)号：US11334382B2

公开(公告)日：2022-05-17

申请号：US16563175

申请日：2019-09-06

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Kshitij Doshi ,  Suraj Prabhakaran ,  Ned M. Smith

IPC: H04L12/66 ,  H04L12/24 ,  H04L12/911 ,  H04L29/08 ,  G06F9/48 ,  G06F16/23 ,  H04L9/06 ,  G06F16/27 ,  H04L9/32 ,  H04L41/12 ,  H04L47/70 ,  H04L67/52 ,  H04L67/60 ,  G06F9/50 ,  G06F21/60 ,  H04L9/08 ,  G06F11/30 ,  G06F9/455

Abstract: Technologies for batching requests in an edge infrastructure include a compute device including circuitry configured to obtain a request for an operation to be performed at an edge location. The circuitry is also configured to determine, as a function of a parameter of the obtained request, a batch that the obtained request is to be assigned to. The batch includes a one or more requests for operations to be performed at an edge location. The circuitry is also configured to assign the batch to a cloudlet at an edge location. The cloudlet includes a set of resources usable to execute the operations requested in the batch.

公开(公告)号：US11232127B2

公开(公告)日：2022-01-25

申请号：US16235202

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Suraj Prabhakaran ,  Ramanathan Sethuraman ,  Timothy Verrall ,  Ned Smith

IPC: G06F16/27 ,  G06F3/06

Abstract: Technologies for providing dynamic persistence of data in edge computing include a device including circuitry configured to determine multiple different logical domains of data storage resources for use in storing data from a client compute device at an edge of a network. Each logical domain has a different set of characteristics. The circuitry is also to configured to receive, from the client compute device, a request to persist data. The request includes a target persistence objective indicative of an objective to be satisfied in the storage of the data. Additionally, the circuitry is configured to select, as a function of the characteristics of the logical domains and the target persistence objective, a logical domain into which to persist the data and provide the data to the selected logical domain.

公开(公告)号：US10970216B2

公开(公告)日：2021-04-06

申请号：US15855104

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Kshitij A. Doshi ,  Francesc Guim Bernat ,  Daniel Rivas Barragan ,  Suraj Prabhakaran

IPC: G06F12/0831 ,  G06F13/16 ,  G06F16/22 ,  G06F12/02

Abstract: An embodiment of a semiconductor package apparatus may include technology to create a tracking structure for a memory controller to track a range of memory addresses of a persistent memory, identify a write request at the memory controller for a memory location within the range of tracked memory addresses, and set a flag in the tracking structure to indicate that the memory location had the identified write request. Other embodiments are disclosed and claimed.

公开(公告)号：US10757757B2

公开(公告)日：2020-08-25

申请号：US16235685

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Dario Sabella ,  Ned M. Smith ,  Neal Oliver ,  Kshitij Arun Doshi ,  Suraj Prabhakaran ,  Francesc Guim Bernat ,  Miltiadis Filippou

IPC: H04W88/18 ,  H04L29/08 ,  H04W12/00 ,  H04W48/08 ,  H04L29/06 ,  H04W4/44 ,  H04W88/16 ,  H04L12/24 ,  G06F9/455 ,  G06F8/70 ,  H04W84/12

Abstract: Various systems and methods for enhancing a distributed computing environment with multiple edge hosts and user devices, including in multi-access edge computing (MEC) network platforms and settings, are described herein. A device of a lifecycle management (LCM) proxy apparatus obtains a request, from a device application, for an application multiple context of an application. The application multiple context for the application is determined. The request from the device application for the application multiple context for the application is authorized. A device application identifier based on the request is added to the application multiple context. A created response for the device application based on the authorization of the request is transmitted to the device application. The response includes an identifier of the application multiple context.

公开(公告)号：US20200076682A1

公开(公告)日：2020-03-05

申请号：US16367626

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Benjamin Graniello ,  Timothy Verrall ,  Andrew J. Herdrich ,  Rashmin Patel ,  Monica Kenguva ,  Brinda Ganesh ,  Alexander Vul ,  Ned M. Smith ,  Suraj Prabhakaran

IPC: H04L12/24

Abstract: Technologies for providing multi-tenant support in edge resources using edge channels include a device that includes circuitry to obtain a message associated with a service provided at the edge of a network. Additionally, the circuitry is to identify an edge channel based on metadata associated with the message. The edge channel has a predefined amount of resource capacity allocated to the edge channel to process the message. Further, the circuitry is to determine the predefined amount of resource capacity allocated to the edge channel and process the message using the allocated resource capacity for the identified edge channel.

公开(公告)号：US10541942B2

公开(公告)日：2020-01-21

申请号：US15941943

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Anil Rao ,  Suraj Prabhakaran ,  Mohan Kumar ,  Karthik Kumar

IPC: H04L12/947 ,  H04L12/66 ,  H04L12/801 ,  H04L12/931

Abstract: Technologies for accelerating edge device workloads at a device edge network include a network computing device which includes a processor platform that includes at least one processor which supports a plurality of non-accelerated function-as-a-service (FaaS) operations and an accelerated platform that includes at least one accelerator which supports a plurality of accelerated FaaS (AFaaS) operation. The network computing device is configured to receive a request to perform a FaaS operation, determine whether the received request indicates that an AFaaS operation is to be performed on the received request, and identify compute requirements for the AFaaS operation to be performed. The network computing device is further configured to select an accelerator platform to perform the identified AFaaS operation and forward the received request to the selected accelerator platform to perform the identified AFaaS operation. Other embodiments are described and claimed.

公开(公告)号：US20190391855A1

公开(公告)日：2019-12-26

申请号：US16563171

申请日：2019-09-06

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Suraj Prabhakaran ,  Timothy Verrall ,  Thomas Willhalm ,  Mark Schmisseur

IPC: G06F9/50 ,  H04L9/08 ,  G06F21/60 ,  G06F16/27

Abstract: Technologies for providing efficient data access in an edge infrastructure include a compute device comprising circuitry configured to identify pools of resources that are usable to access data at an edge location. The circuitry is also configured to receive a request to execute a function at an edge location. The request identifies a data access performance target for the function. The circuitry is also configured to map, based on a data access performance of each pool and the data access performance target of the function, the function to a set of the pools to satisfy the data access performance target.

公开(公告)号：US20190230154A1

公开(公告)日：2019-07-25

申请号：US16369413

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Kshitij Doshi ,  Francesc Guim Bernat ,  Suraj Prabhakaran

IPC: H04L29/08 ,  H04L29/06

Abstract: Technologies for matching security requirements for a function-as-a-service (FaaS) function request to an edge resource having security features matching the security requirements are disclosed. According to one embodiment of the present disclosure, an edge gateway device receives, from an edge device, a request to execute an accelerated function. The edge gateway device selects, as a function of one or more security requirements requested by the edge device, an edge resource to fulfill the request. The edge gateway device transmits the request to the edge resource to fulfill the request of the edge device, according to the one or more security requirements.