公开(公告)号：US20070106826A1

公开(公告)日：2007-05-10

申请号：US11267498

申请日：2005-11-07

Applicant: Peter Chia ,  Chad Tsai ,  Jiin Lai ,  Edward Su ,  Chih-Kuo Kao

Inventor： Peter Chia ,  Chad Tsai ,  Jiin Lai ,  Edward Su ,  Chih-Kuo Kao

IPC: G06F13/36

CPC classification number: G06F13/36

Abstract: The present computing system using PCI-E architecture includes at least one first PCI-E port, a first port-arbiter, a first URD logic, a microprocessor, a DARD logic and a device arbiter. The first port-arbiter receives a data from the first PCI-E port. The first URD logic is coupled to said first port-arbiter. The first URD logic includes an onboard range table and a PCI-E device range table for detecting the data of onboard access or peer-to-peer access. The microprocessor receives and processes the data from the first URD logic for said onboard access. The DARD logic receives the data from the microprocessor. The DARD logic decodes a device range of a downstream request of the data. The device arbiter is coupled to the DARD logic and the first URD logic for dispatching the data to one of the first PCI-E port.

Abstract translation: 使用PCI-E架构的本计算系统包括至少一个第一PCI-E端口，第一端口仲裁​​器，第一URD逻辑，微处理器，DARD逻辑和设备仲裁器。 第一个端口仲裁器从第一个PCI-E端口接收数据。 第一URD逻辑耦合到所述第一端口仲裁​​器。 第一个URD逻辑包括板载范围表和PCI-E设备范围表，用于检测板上访问或对等访问的数据。 微处理器接收并处理来自用于所述板载存取的第一URD逻辑的数据。 DARD逻辑从微处理器接收数据。 DARD逻辑解码数据的下游请求的设备范围。 设备仲裁器耦合到DARD逻辑和第一个URD逻辑，用于将数据分配到第一个PCI-E端口之一。

公开(公告)号：US20070011390A1

公开(公告)日：2007-01-11

申请号：US11531282

申请日：2006-09-13

Applicant: Jiin Lai ,  Chad Tsai ,  Ju Zhang ,  Andrew Chuang ,  Andrew Su

Inventor： Jiin Lai ,  Chad Tsai ,  Ju Zhang ,  Andrew Chuang ,  Andrew Su

IPC: G06F13/20

CPC classification number: G06F13/385

Abstract: A method and related apparatus used for controlling a peripheral device to transfer data to a bus. The peripheral device has a bus interface circuit and a controller. The method includes storing data outputted from the controller into a first storage block of the bus interface circuit, utilizing the bus interface circuit to simultaneously control the first storage block to output its stored data to the bus and control a second storage block of the bus interface circuit to store data outputted from the controller, and utilizing the bus interface circuit to control the second storage block to output its stored data to the bus.

Abstract translation: 一种用于控制外围设备将数据传送到总线的方法和相关装置。 外围设备具有总线接口电路和控制器。 该方法包括将从控制器输出的数据存储到总线接口电路的第一存储块中，利用总线接口电路同时控制第一存储块以将其存储的数据输出到总线并控制总线接口的第二存储块 存储从控制器输出的数据的电路，利用总线接口电路来控制第二存储块，将其存储的数据输出到总线。

公开(公告)号：US07124214B2

公开(公告)日：2006-10-17

申请号：US10707806

申请日：2004-01-14

Applicant: Jiin Lai ,  Chad Tsai ,  Ju Zhang ,  Andrew Chuang ,  Andrew Su

Inventor： Jiin Lai ,  Chad Tsai ,  Ju Zhang ,  Andrew Chuang ,  Andrew Su

IPC: G06F3/00

CPC classification number: G06F13/385

Abstract: A method and related apparatus used for controlling a peripheral device to transfer data to a bus. The peripheral device has a bus interface circuit and a controller. The method includes storing data outputted from the controller into a first storage block of the bus interface circuit, utilizing the bus interface circuit to simultaneously control the first storage block to output its stored data to the bus and control a second storage block of the bus interface circuit to store data outputted from the controller, and utilizing the bus interface circuit to control the second storage block to output its stored data to the bus.

Abstract translation: 一种用于控制外围设备将数据传送到总线的方法和相关装置。 外围设备具有总线接口电路和控制器。 该方法包括将从控制器输出的数据存储到总线接口电路的第一存储块中，利用总线接口电路同时控制第一存储块以将其存储的数据输出到总线并控制总线接口的第二存储块 存储从控制器输出的数据的电路，利用总线接口电路来控制第二存储块，将其存储的数据输出到总线。

公开(公告)号：US20060174151A1

公开(公告)日：2006-08-03

申请号：US11048191

申请日：2005-02-01

Applicant: Ruei-Ling Lin ,  Jiin Lai ,  Hung-Yi Kuo

Inventor： Ruei-Ling Lin ,  Jiin Lai ,  Hung-Yi Kuo

IPC: G06F1/26 ,  G06F1/06

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/172

Abstract: A core logic coupled to a main memory of a computer, comprising an analyzer and a power management unit. The analyzer monitors access request traffic load of main memory. The power management unit employs various power performance trade-off activities with the knowledge of the monitored traffic load according to the state machine.

Abstract translation: 耦合到计算机的主存储器的核心逻辑，包括分析器和电源管理单元。 分析仪监控主存储器的访问请求流量负载。 电力管理单元根据状态机采用各种电力性能权衡活动，了解监控的业务负载。

公开(公告)号：US20060095632A1

公开(公告)日：2006-05-04

申请号：US11257259

申请日：2005-10-24

Applicant: Ruei-Ling Lin ,  Jiin Lai

Inventor： Ruei-Ling Lin ,  Jiin Lai

IPC: G06F13/36

CPC classification number: G06F13/4208

Abstract: In a data transmission coordinating method, information associated with a first transmission standard of the bridge chip is read from a memory unit of the computer system. A first signal from the bridge chip is issued to the central processing unit to inform the central processing unit of the first transmission standard of the bridge chip. A second signal is issued from the central processing unit to the bridge chip to inform the bridge chip of a second transmission standard of the central processing unit. A commonly operable transmission standard is coordinated for both the central processing unit and the bridge chip according to the first transmission standard and the second transmission standard.

Abstract translation: 在数据传输协调方法中，从计算机系统的存储器单元读取与桥芯片的第一传输标准相关联的信息。 来自桥芯片的第一信号被发送到中央处理单元，以通知中央处理单元桥接芯片的第一传输标准。 从中央处理单元向桥接芯片发出第二信号，以向桥接芯片通知中央处理单元的第二传输标准。 根据第一传输标准和第二传输标准，为中央处理单元和桥接芯片两者协调通用的传输标准。

公开(公告)号：US20050289317A1

公开(公告)日：2005-12-29

申请号：US10906748

申请日：2005-03-04

Applicant: Ming-Shi Liou ,  Bowei Hsieh ,  Jiin Lai

Inventor： Ming-Shi Liou ,  Bowei Hsieh ,  Jiin Lai

IPC: G06F12/00 ,  G06F13/16

CPC classification number: G06F13/1684 ,  G11C2207/2281

Abstract: A method for utilizing the multi-channel transmission bandwidth in an asymmetrically arranged memory is provides. The present invention defines symmetrically arranged parts of the memory ranks of the memory as a virtual ranks. If data is stored in symmetrically arranged memory ranks of the memory, channels corresponding to the symmetrically arranged memory ranks could be simultaneously utilized to transfer data. If data is stored in an asymmetrically arranged memory rank of the memory, the channel corresponding to the asymmetrically arranged memory rank could only be utilized to transfer data.

Abstract translation: 提供了一种在不对称布置的存储器中利用多通道传输带宽的方法。 本发明将存储器的存储器级别的对称布置部分定义为虚拟等级。 如果数据存储在存储器的对称布置的存储器级中，则对应于对称排列的存储器级别的通道可以同时用于传送数据。 如果数据被存储在存储器的不对称排列的存储器级中，则对应于不对称布置的存储器级的通道只能用于传送数据。

公开(公告)号：US06944730B2

公开(公告)日：2005-09-13

申请号：US10352090

申请日：2003-01-28

Applicant: Jiin Lai ,  Sheng-Chung Wu

Inventor： Jiin Lai ,  Sheng-Chung Wu

IPC: G06F13/16 ,  G06F12/00

CPC classification number: G06F13/161

Abstract: A read/write scheduling apparatus of controller chip and method for the same. The read/write scheduling apparatus is used for arbitrating a plurality of read and write requests from a CPU to access a memory unit. The read request has higher priority in a host bandwidth limited case and the write requests in write queues are not sent until a predetermined amount of write requests are accumulated. In a DRAM bandwidth limited case, the read and the write requests have the same priority. The scheduling apparatus counts the number of the read and write requests to the memory unit within a predetermined time, the operation is changed to DRAM bandwidth limited case in case that the counted number is larger than a predetermined number.

Abstract translation: 一种控制器芯片的读/写调度装置及其方法。 读/写调度装置用于仲裁来自CPU的多个读和写请求以访问存储单元。 读取请求在主机带宽限制情况下具有较高的优先级，并且在发送预定量的写入请求之前不写入队列中的写入请求。 在DRAM带宽有限的情况下，读取和写入请求具有相同的优先级。 调度装置在预定时间内对存储器单元的读取和写入请求的数量进行计数，在计数的数量大于预定数量的情况下，将操作改变为DRAM带宽限制的情况。

公开(公告)号：US06738880B2

公开(公告)日：2004-05-18

申请号：US09878896

申请日：2001-06-11

Applicant: Jiin Lai ,  Chia-Hsin Chen ,  Nai-Shung Chang

Inventor： Jiin Lai ,  Chia-Hsin Chen ,  Nai-Shung Chang

IPC: G06F1300

CPC classification number: G11C7/1057 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/1087

Abstract: A buffer for varying data access speed. Combining the buffer with a memory such as a double data rate synchronous dynamic random access memory, the data transmission rate of a memory system can be enhanced. The buffer is coupled with a control chip set and several memory modules to provide functions of data analysis and assembly to satisfy a two-way data transmission interface and to obtain a higher data transmission rate. The buffer also has the function of isolating the electric connection between two sides. A single signal interface from a memory module can be converted to a complementary source synchronous signal by the buffer, so that a high-speed data transmission can be achieved. A memory system can apply several of such buffers to achieve an even higher data transmission speed.

Abstract translation: 一种用于改变数据访问速度的缓冲区。 将缓冲器与诸如双倍数据速率同步动态随机存取存储器的存储器组合，可以提高存储器系统的数据传输速率。 缓冲器与控制芯片组和多个存储器模块耦合，以提供数据分析和组装的功能，以满足双向数据传输接口并获得更高的数据传输速率。 缓冲器还具有隔离两侧电气连接的功能。 来自存储器模块的单个信号接口可以由缓冲器转换成互补源同步信号，从而可以实现高速数据传输。 存储器系统可以应用若干这样的缓冲器以实现甚至更高的数据传输速度。

公开(公告)号：US06721833B2

公开(公告)日：2004-04-13

申请号：US09735412

申请日：2000-12-12

Applicant: Jiin Lai ,  Chau-Chad Tsai ,  Sheng-Chang Peng ,  Chi-Che Tsai

Inventor： Jiin Lai ,  Chau-Chad Tsai ,  Sheng-Chang Peng ,  Chi-Che Tsai

IPC: G06F1336

CPC classification number: G06F13/36

Abstract: A bus arbitration method within a control chipset, The control chipset further comprises a first control chip and a second control chip, data are transferred between the first and the second control chips through a bus, the bus comprises a bidirectional bus The first control chip usually control the authority to use the bus, however the second control chip has higher priority to use the bus. Accompany with a bus specification without waiting cycle, to arbitrate the authority to use the bus can be done fast and without errors. Therefore, no GNT signal line is required and the arbitration time reduces.

Abstract translation: 一种控制芯片组内的总线仲裁方法，控制芯片组还包括第一控制芯片和第二控制芯片，数据通过总线在第一和第二控制芯片之间传输，总线包括双向总线第一控制芯片通常 控制使用总线的权限，但第二个控制芯片具有使用总线的优先级。 伴随总线规格无等待周期，仲裁权限使用总线可以快速，毫无错误地完成。 因此，不需要GNT信号线，仲裁时间缩短。

公开(公告)号：US06684284B1

公开(公告)日：2004-01-27

申请号：US09718811

申请日：2000-11-22

Applicant: Jiin Lai ,  Chau-Chad Tsai ,  Sheng-Chang Peng ,  Chi-Che Tsai

Inventor： Jiin Lai ,  Chau-Chad Tsai ,  Sheng-Chang Peng ,  Chi-Che Tsai

IPC: G06F944

CPC classification number: G06F13/4027

Abstract: A data transaction method between control chips. Data buffers of the control chips of the control chipset have fixed size and amount. In addition, read/write acknowledge commands are asserted in sequence according to read/write commands, by which the control chips can detect the status of the buffers within another control chips. When a control chip asserts a command, the corresponding data must be ready in advance. Therefore, the signal line for providing the waiting status, data transaction cycle and stop/retry protocol can be omitted. Accordingly, commands or data can be continuously transmitted without waiting, stop or retry, the performance is improved.

Abstract translation: 控制芯片之间的数据交易方法。 控制芯片组的控制芯片的数据缓冲器具有固定的尺寸和数量。 此外，读/写确认命令根据读/写命令依次被断言，通过该命令，控制芯片可以检测另一个控制芯片内的缓冲器的状态。 当控制芯片发出命令时，相应的数据必须提前准备就绪。 因此，可以省略用于提供等待状态，数据事务周期和停止/重试协议的信号线。 因此，可以连续发送命令或数据，而无需等待，停止或重试，提高性能。