公开(公告)号：US20120168829A1

公开(公告)日：2012-07-05

申请号：US13143591

申请日：2011-01-27

Applicant: Huicai Zhong ,  Qingqing Liang ,  Da Yang ,  Chao Zhao

Inventor： Huicai Zhong ,  Qingqing Liang ,  Da Yang ,  Chao Zhao

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/4983 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/7845

Abstract: The invention provides a MOS transistor and a method for forming the MOS transistor. The MOS transistor includes a semiconductor substrate; a gate stack on the semiconductor substrate, and including a gate dielectric layer and a gate electrode on the semiconductor substrate in sequence; a source region and a drain region, respectively at sidewalls of the gate stack sidewalls of the gate stack and in the semiconductor; sacrificial metal spacers on sidewalls of the gate stack sidewalls of the gate stack, and having tensile stress or compressive stress. This invention scales down the equivalent oxide thickness, improves uniformity of device performance, raises carrier mobility and promotes device performance.

Abstract translation: 本发明提供一种MOS晶体管和一种用于形成MOS晶体管的方法。 MOS晶体管包括半导体衬底; 半导体衬底上的栅极堆叠，并且在半导体衬底上依次包括栅极介电层和栅电极; 源极区和漏极区，分别位于栅极堆叠的栅极堆叠侧壁的侧壁和半导体中; 牺牲金属间隔物在栅堆叠的栅堆叠侧壁的侧壁上，并且具有拉应力或压应力。 本发明缩小了等效氧化物厚度，改善了器件性能的均匀性，提高了载流子迁移率并提高了器件性能。

公开(公告)号：US20120146223A1

公开(公告)日：2012-06-14

申请号：US13139063

申请日：2011-01-27

Applicant: Chao Zhao ,  Wenwu Wang

Inventor： Chao Zhao ,  Wenwu Wang

IPC: H01L21/28 ,  H01L23/48

CPC classification number: H01L27/101 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76873 ,  H01L23/53238 ,  H01L27/2436 ,  H01L29/78 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1633 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A manufacturing method of a MOS device with memory function is provided, which includes: providing a semiconductor substrate, a surface of the semiconductor substrate being covered by a first dielectric layer, a metal interconnect structure being formed in the first dielectric layer; forming a second dielectric layer overlying a surface of the first dielectric layer and the metal interconnect structure; forming an opening in the second dielectric layer, a bottom of the opening revealing the metal interconnect structure; forming an alloy layer at the bottom of the opening, material of the alloy layer containing copper and other metal; and performing a thermal treatment to the alloy layer and the metal interconnect structure to form, on the surface of the metal interconnect structure, a compound layer containing oxygen element. The compound layer containing oxygen element and the MOS device formed in the semiconductor substrate constitute a MOS device with memory function. The method provides a processing which has high controllability and improves the performance of devices.

Abstract translation: 提供具有记忆功能的MOS器件的制造方法，其包括：提供半导体衬底，半导体衬底的表面被第一介电层覆盖，金属互连结构形成在第一介电层中; 形成覆盖在所述第一电介质层和所述金属互连结构的表面上的第二电介质层; 在所述第二介电层中形成开口，所述开口的底部露出所述金属互连结构; 在开口的底部形成合金层，含有铜等金属的合金层的材料; 对合金层和金属互连结构进行热处理，在金属互连结构的表面形成含有氧元素的化合物层。 包含氧元素的化合物层和形成在半导体衬底中的MOS器件构成具有记忆功能的MOS器件。 该方法提供了具有高可控性和提高设备性能的处理。

公开(公告)号：US20120135589A1

公开(公告)日：2012-05-31

申请号：US13142736

申请日：2011-04-12

Applicant: Tao Yang ,  Jinbiao Liu ,  Xiaobin He ,  Chao Zhao ,  Dapeng Chen

Inventor： Tao Yang ,  Jinbiao Liu ,  Xiaobin He ,  Chao Zhao ,  Dapeng Chen

IPC: H01L21/306 ,  H01L21/304 ,  H01L21/28

CPC classification number: H01L21/31053 ,  H01L21/31155 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/78

Abstract: The present invention provides a chemical-mechanical planarization method and a method for fabricating a metal gate in gate last process. The chemical-mechanical planarization method includes: providing a substrate including a gate and source/drain regions on the sides of the gate, the gate and the source/drain regions being overlay by an insulating layer, and the insulating layer including a protruding part above the gate and a recessed part above a surface of the substrate between gates; selectively doping the insulating layer such that only the protruding part is doped; and performing CMP on the substrate after doping, to remove the protruding part and planarize the surface of the substrate. By selectively doping the insulating layer, the method makes only the protruding part of the insulating layer doped, enhancing the corrosive attacks on the material of the protruding part by the slurry in the CMP, and increasing the removal rate of the material of the protruding part by the CMP, thereby improving the within-die uniformity of the process, consequently, there will not be excess metal in the insulating layer between gates, thereby preventing device short circuit risk induced by POP CMP process.

Abstract translation: 本发明提供一种化学机械平面化方法及其制造方法。 化学机械平面化方法包括：在栅极的侧面设置包括栅极和源极/漏极区域的衬底，栅极和源极/漏极区域被绝缘层覆盖，并且绝缘层包括在上方的突出部分 栅极和位于栅极之间的衬底表面上方的凹陷部分; 选择性地掺杂绝缘层，使得只有突出部分被掺杂; 并且在掺杂之后在衬底上执行CMP以去除突出部分并使衬底的表面平坦化。 通过选择性地掺杂绝缘层，该方法仅使掺杂的绝缘层的突出部分增加了CMP中的浆料对突出部分的材料的腐蚀攻击，并且增加了突出部分的材料的去除速率 通过CMP，从而提高了工艺的管芯内均匀性，因此在栅极之间的绝缘层中不会有过多的金属，从而防止POP CMP工艺引起的器件短路风险。

公开(公告)号：US20120112358A1

公开(公告)日：2012-05-10

申请号：US13120792

申请日：2011-02-17

Applicant: Qingqing Liang ,  Huicai Zhong ,  Chao Zhao ,  Huilong Zhu

Inventor： Qingqing Liang ,  Huicai Zhong ,  Chao Zhao ,  Huilong Zhu

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L25/50 ,  H01L21/6835 ,  H01L23/481 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A stack-type semiconductor device includes a semiconductor substrate; and a plurality of wafer assemblies arranged in various levels on the semiconductor substrate, in which the wafer assembly in each level includes an active part and an interconnect part, and the active part and the interconnect part each have conductive through vias, wherein the conductive through vias in the active part are aligned with the conductive through vias in the interconnect part in a vertical direction, so that the active part in each level is electrically coupled with the active part in the previous level and/or the active part in the next level by the conductive through vias. Such a stack-type semiconductor device and the related methods can be applied in a process after the FEOL or in a semiconductor chip packaging process and provide a 3-dimensional semiconductor device of high integration and high reliability.

Abstract translation: 堆叠型半导体器件包括半导体衬底; 以及在所述半导体衬底上以各种级别布置的多个晶片组件，其中每个级中的所述晶片组件包括有源部分和互连部分，并且所述有源部分和所述互连部件各自具有导电通孔，其中所述导电通孔 有源部分中的通孔在垂直方向上与互连部分中的导电通孔对准，使得每个电平中的有源部分与先前电平中的有源部分和/或下一级的有源部分电耦合 通过导电通孔。 这种叠层型半导体器件及相关方法可以在FEOL之后的工艺中或半导体芯片封装工艺中应用，并提供高集成度和高​​可靠性的三维半导体器件。

公开(公告)号：US20120043592A1

公开(公告)日：2012-02-23

申请号：US13132985

申请日：2011-02-23

Applicant: Chao Zhao ,  Wenwu Wang ,  Huilong Zhu

Inventor： Chao Zhao ,  Wenwu Wang ,  Huilong Zhu

IPC: H01L29/772 ,  H01L21/768

CPC classification number: H01L23/485 ,  H01L21/76847 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a semiconductor device. The semiconductor device comprises contact plugs that comprise a first contact plug formed by a first barrier layer arranged on the source and drain regions and a tungsten layer arranged on the first barrier layer; and second contact plugs comprising a second barrier layer arranged on both of the metal gate and the first contact plug and a conductive layer arranged on the second barrier layer. The conductivity of the conductive layer is higher than that of the tungsten layer. A method for forming the semiconductor device is also provided. The present invention provides the advantage of enhancing the reliability of the device when using the copper contact technique.

Abstract translation: 本发明提供一种半导体器件。 半导体器件包括接触插塞，其包括由布置在源区和漏区上的第一阻挡层和布置在第一阻挡层上的钨层形成的第一接触插塞; 以及第二接触插塞，其包括布置在金属栅极和第一接触插塞两者上的第二阻挡层和布置在第二阻挡层上的导电层。 导电层的导电性高于钨层。 还提供了一种用于形成半导体器件的方法。 本发明提供了当使用铜接触技术时提高器件的可靠性的优点。