公开(公告)号：US07018889B2

公开(公告)日：2006-03-28

申请号：US10869128

申请日：2004-06-16

申请人： John D. Porter ,  William N. Thompson

发明人： John D. Porter ,  William N. Thompson

IPC分类号： H01L21/8234 ,  H01L21/8244

CPC分类号： H01L27/1104 ,  G11C11/412

摘要： An SRAM memory cell is provided having a pair of cross-coupled CMOS inverters. The sources of the pull-up transistors forming each of the CMOS inverters are coupled to VCC through parasitic resistance of the substrate in which each is formed. The source of the p-type pull-up transistor is therefore always at a potential less than or equal to the potential of the N-well such that the emitter-base junction of the parasitic PNP transistor cannot become forward biased and latch-up cannot occur.

摘要翻译： 提供具有一对交叉耦合CMOS反相器的SRAM存储单元。 形成每个CMOS反相器的上拉晶体管的源极通过其中形成各自的衬底的寄生电阻耦合到V CC。 因此，p型上拉晶体管的源极总是处于小于或等于N阱的电位的电位，使得寄生PNP晶体管的发射极 - 基极结不能变为正向偏置，并且闭锁不能 发生。

公开(公告)号：US06958661B2

公开(公告)日：2005-10-25

申请号：US10409460

申请日：2003-04-08

申请人： William N. Thompson ,  John D. Porter ,  Larren Gene Weber

发明人： William N. Thompson ,  John D. Porter ,  Larren Gene Weber

IPC分类号： H03H11/28 ,  H03H17/02 ,  H03H11/30

CPC分类号： G11C7/1051 ,  G11C7/1069 ,  H03H7/40 ,  H03H11/245 ,  H03H11/28 ,  H03H17/0263

摘要： A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an arbitrary search value within the range, performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range. In one embodiment, the method of finding an unknown value within a range of values is applied to impedance matching. In this embodiment, the output impedance of a pin on an integrated circuit is automatically matched to the impedance of the load connected to it. The output driver has a controllable impedance that can be adjusted within a specific range of impedances to match the external load impedance it is to drive.

摘要翻译： 公开了一种从值范围内找到未知值的方法，其将范围划分为加权子范围，然后从该范围内的任意搜索值开始，执行多个简单比较，以确定每个子范围的值， 导致与目标值匹配。 该方法还可以检测目标值在范围之外的情况。 在一个实施例中，将在值范围内找到未知值的方法应用于阻抗匹配。 在本实施例中，集成电路上的引脚的输出阻抗与连接到其的负载的阻抗自动匹配。 输出驱动器具有可控阻抗，可以在特定阻抗范围内进行调节，以匹配驱动的外部负载阻抗。

公开(公告)号：US06917222B2

公开(公告)日：2005-07-12

申请号：US10336527

申请日：2003-01-03

申请人： John D. Porter ,  Dean D. Gans ,  Larren G. Weber

发明人： John D. Porter ,  Dean D. Gans ,  Larren G. Weber

IPC分类号： H03K19/017 ,  H03K19/00

CPC分类号： H03K19/01721

摘要： The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the present invention include inverters, buffers, NOR gates and NAND gates for rapidly propagating a selected “fast” edge of an input signal. Additional embodiments include pulse stretchers, memory devices, substrates, computer systems and methods incorporating the skewed logic devices of the present invention. Each embodiment of a skewed logic device of the present invention is configured to propagate either a fast rising edge or fast falling edge of an output signal, i.e., the “fast” edge, at rates comparable to those of domino logic. An advantage of the skewed logic devices of the present invention over conventional CMOS logic devices is rapid edge propagation. Additionally, virtually all of the input gate loading is devoted to the fast edge being propagated. Additionally, the reset networks, as disclosed herein, are buffered by at least two gates, thus reducing loading seen by the input or the output of the skewed logic device.

摘要翻译： 本发明包括具有非常偏斜的跳变点的数字逻辑器件和用于快速传播信号边缘的复位电路。 根据本发明的偏斜逻辑器件的实施例包括用于快速传播输入信号的所选择的“快速”边沿的反相器，缓冲器，或非门和“与非”门。 另外的实施例包括脉冲展开器，存储器件，衬底，计算机系统和结合本发明的倾斜逻辑器件的方法。 本发明的倾斜逻辑器件的每个实施例被配置为以与多米诺逻辑的速率相当的速率传播输出信号的快速上升沿或快速下降沿，即“快速”边沿。 与传统CMOS逻辑器件相比，本发明的偏斜逻辑器件的优点是快速的边沿传播。 此外，实际上所有的输入门加载都用于传播的快速边缘。 另外，如本文公开的复位网络由至少两个门缓冲，从而减少由偏斜逻辑器件的输入或输出所看到的负载。

公开(公告)号：US06809968B2

公开(公告)日：2004-10-26

申请号：US10368068

申请日：2003-02-18

申请人： Kenneth W. Marr ,  John D. Porter

发明人： Kenneth W. Marr ,  John D. Porter

IPC分类号： G11C700

CPC分类号： G11C11/412 ,  G11C5/147 ,  G11C11/417

摘要： Systems and methods are provided for a temperature-compensated threshold voltage VT. The stability problems associated with temperature changes are reduced for LL4TCMOS SRAM cells by providing a temperature-compensated VTN. According to one embodiment, a temperature-based modulation of a VBB potential back-biases a triple-well transistor with a temperature-compensated voltage to provide the pull-down transistor with a temperature-compensated VTN that is flat or relatively flat with respect to temperature. One embodiment provides a bias generator, including a charge pump coupled to a body terminal of the transistor(s), and a comparator coupled to the charge pump. The comparator includes a first input that receives a reference voltage, a second input that receives a VT-dependent voltage, and an output that presents a control signal to the charge pump and causes the charge pump to selectively charge the body terminal of the transistor to compensate for temperature changes.

摘要翻译： 为温度补偿阈值电压VT提供系统和方法。 通过提供温度补偿VTN，LL4TCMOS SRAM单元的温度变化相关的稳定性问题减少了。 根据一个实施例，VBB电位的基于温度的调制利用温度补偿电压对三阱晶体管进行背偏置，以向下拉晶体管提供相对于平坦或相对平坦的温度补偿VTN 温度。 一个实施例提供了一种偏置发生器，包括耦合到晶体管的主体端子的电荷泵和耦合到电荷泵的比较器。 比较器包括接收参考电压的第一输入端，接收VT相关电压的第二输入端和向电荷泵呈现控制信号的输出，并使电荷泵有选择地将晶体管的体电极充电至 补偿温度变化。

公开(公告)号：US06741027B1

公开(公告)日：2004-05-25

申请号：US09895699

申请日：2001-06-29

申请人： William J. Cummings ,  Kris E. Sahlstrom ,  Shiyou Pei ,  Bob L. Mackey ,  Arthur J. Learn ,  John D. Porter ,  Theodore S. Fahlen

发明人： William J. Cummings ,  Kris E. Sahlstrom ,  Shiyou Pei ,  Bob L. Mackey ,  Arthur J. Learn ,  John D. Porter ,  Theodore S. Fahlen

IPC分类号： H01J162

CPC分类号： H01J29/94 ,  H01J1/304 ,  H01J29/06 ,  H01J29/085 ,  H01J2201/02 ,  H01J2329/00 ,  H01J2329/863 ,  H01J2329/8645 ,  H01J2329/8665

摘要： A protected faceplate structure of a field emission display device is disclosed in one embodiment. Specifically, in one embodiment, the present invention recites a faceplate of a field emission display device wherein the faceplate of the field emission display device is adapted to have phosphor containing areas disposed above one side thereof. The present embodiment is further comprised of a barrier layer which is disposed over the one side of said faceplate which is adapted to have phosphor containing areas disposed thereabove. The barrier layer of the present embodiment is adapted to prevent degradation of the faceplate. Specifically, the barrier layer of the present embodiment is adapted to prevent degradation of the faceplate due to electron bombardment by electrons directed towards the phosphor containing areas.

摘要翻译： 在一个实施例中公开了场致发射显示装置的受保护的面板结构。 具体地说，在一个实施例中，本发明叙述场致发射显示装置的面板，其中场致发射显示装置的面板适于具有设置在其一侧上方的荧光体容纳区域。 本实施例还包括阻挡层，该阻挡层设置在所述面板的一侧上，其适于具有设置在其上的荧光体容纳区域。 本实施例的阻挡层适于防止面板的劣化。 具体而言，本实施方式的阻挡层适于防止由于朝向含荧光体区域的电子的电子轰击引起的面板的劣化。

公开(公告)号：US06724218B2

公开(公告)日：2004-04-20

申请号：US10336355

申请日：2003-01-03

申请人： John D. Porter ,  Dean D. Gans ,  Larren G. Weber

发明人： John D. Porter ,  Dean D. Gans ,  Larren G. Weber

IPC分类号： H03K190175

CPC分类号： H03K19/01721

摘要： The invention includes digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges. Embodiments of skewed logic devices in accordance with the present invention include inverters, buffers, NOR gates and NAND gates for rapidly propagating a selected “fast” edge of an input signal. Additional embodiments include pulse stretchers, memory devices, substrates, computer systems and methods incorporating the skewed logic devices of the present invention. Each embodiment of a skewed logic device of the present invention is configured to propagate either a fast rising edge or fast falling edge of an output signal, i.e., the “fast” edge, at rates comparable to those of domino logic. An advantage of the skewed logic devices of the present invention over conventional CMOS logic devices is rapid edge propagation. Additionally, virtually all of the input gate loading is devoted to the fast edge being propagated. Additionally, the reset networks, as disclosed herein, are buffered by at least two gates, thus reducing loading seen by the input or the output of the skewed logic device.

摘要翻译： 本发明包括具有非常偏斜的跳变点的数字逻辑器件和用于快速传播信号边缘的复位电路。 根据本发明的偏斜逻辑器件的实施例包括用于快速传播输入信号的所选择的“快速”边沿的反相器，缓冲器，或非门和“与非”门。 另外的实施例包括脉冲展开器，存储器件，衬底，计算机系统和结合本发明的倾斜逻辑器件的方法。 本发明的倾斜逻辑器件的每个实施例被配置为以与多米诺逻辑的速率相当的速率传播输出信号的快速上升沿或快速下降沿，即“快速”边沿。 与传统CMOS逻辑器件相比，本发明的偏斜逻辑器件的优点是快速的边沿传播。 此外，实际上所有的输入门加载都用于传播的快速边缘。 此外，如本文所公开的复位网络由至少两个门缓冲，从而减少由倾斜逻辑器件的输入或输出所看到的负载。

公开(公告)号：US06545560B1

公开(公告)日：2003-04-08

申请号：US09924658

申请日：2001-08-08

申请人： William N. Thompson ,  John D. Porter ,  Larren Gene Weber

发明人： William N. Thompson ,  John D. Porter ,  Larren Gene Weber

IPC分类号： H03H1130

CPC分类号： G11C7/1051 ,  G11C7/1069 ,  H03H7/40 ,  H03H11/245 ,  H03H11/28 ,  H03H17/0263

摘要： A method of finding an unknown value from within a range of values is disclosed that divides the range into weighted subranges and then, beginning with an arbitrary search value within the range, performs a number of simple comparisons to determine the value for each subrange that will result in a match with the target value. This method can also detect those cases where the target value lies outside the range. In one embodiment, the method of finding an unknown value within a range of values is applied to impedance matching. In this embodiment, the output impedance of a pin on an integrated circuit is automatically matched to the impedance of the load connected to it. The output driver has a controllable impedance that can be adjusted within a specific range of impedances to match the external load impedance it is to drive.

公开(公告)号：US06516363B1

公开(公告)日：2003-02-04

申请号：US09369515

申请日：1999-08-06

申请人： John D. Porter ,  William N. Thompson ,  Larren Gene Weber

发明人： John D. Porter ,  William N. Thompson ,  Larren Gene Weber

IPC分类号： G06F1314

CPC分类号： G11C7/106 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/1066

摘要： Systems, data paths and methods of transferring data. By utilizing the systems, data paths, and methods, data can be transferred at a single or double rate. One embodiment of the present invention provides a system having a data unit, an output register, and a holding register. The output register is coupled to the data unit. The holding register is coupled to the data unit and the output register. Data from the data unit is passed to the output register and the holding register substantially simultaneously and data from the holding register is then passed to the output register. Data can be output from the output register.

摘要翻译： 系统，数据路径和传输数据的方法。 通过利用系统，数据路径和方法，可以以单速率或双速率传输数据。 本发明的一个实施例提供一种具有数据单元，输出寄存器和保持寄存器的系统。 输出寄存器耦合到数据单元。 保持寄存器耦合到数据单元和输出寄存器。 来自数据单元的数据基本上同时传送到输出寄存器和保持寄存器，然后将来自保持寄存器的数据传递给输出寄存器。 数据可以从输出寄存器输出。

公开(公告)号：US06323590B1

公开(公告)日：2001-11-27

申请号：US09398369

申请日：1999-09-16

申请人： Chungdee Pong ,  John D. Porter ,  Theodore S. Fahlen ,  Christopher J. Curtin ,  Robert G. Neimeyer ,  Paul N. Ludwig

发明人： Chungdee Pong ,  John D. Porter ,  Theodore S. Fahlen ,  Christopher J. Curtin ,  Robert G. Neimeyer ,  Paul N. Ludwig

IPC分类号： H01J2902

CPC分类号： H01J61/305 ,  H01J9/185 ,  H01J9/242 ,  H01J9/261 ,  H01J29/028 ,  H01J29/864 ,  H01J31/123 ,  H01J2329/863 ,  H01J2329/864 ,  H01J2329/8645 ,  H01J2329/8665

摘要： A flat panel display and a method for forming a flat panel display. In one embodiment, the flat panel display includes a wall which is held in place by a structure formed either on the faceplate or on the backplate. In one embodiment the supporting structure is formed by two adjacent walls that form a slot which mechanically restrains the wall. In another embodiment a slot is formed within the faceplate and the walls of the slot mechanically restrain the wall. In one embodiment wall segments are inserted into supporting structures that mechanically restrain each wall segment. In another embodiment a UV curable or a heat curable adhesive is used to maintain walls in their proper alignment and position. In yet another embodiment a conductive material is melted so as to bond conductive lines located on the wall and conductive lines located on the faceplate. This bond electrically connects the conductive lines located on the wall and the conductive lines located on the faceplate and maintains the wall in the proper alignment. The present invention eliminates the need for feet which attach to individual walls for maintaining the walls in the proper alignment.

公开(公告)号：US06288483B1

公开(公告)日：2001-09-11

申请号：US09240351

申请日：1999-01-29

申请人： Duane A. Haven ,  Arthur J. Learn ,  John D. Porter

发明人： Duane A. Haven ,  Arthur J. Learn ,  John D. Porter

IPC分类号： H01J2910

CPC分类号： H01J29/085 ,  H01J31/127

摘要： A light-emitting structure contains a plate (20), light-emissive regions (34R, 36G, and 38B) overlying the plate, and a dark region (40DR/46DC, 40IR/56DC, 60DR/66DC, or 76DR/80DR/80DC) overlying the plate and laterally surrounding each light-emissive region. In one aspect, the dark region is formed with (a) multiple first strips (40DR, 40IR, 60DR, or 76DR) extending in one direction and (b) multiple second strips (46DC, 56DC, 66DC, or 80DC) extending in another direction and also extending further away from the plate than the first strips. In another aspect, the dark region contains trapezoidally profiled strips (86), each having a width profile shaped like an upright trapezoid.

摘要翻译： 发光结构包含板（20），覆盖板上的发光区域（34R，36G和38B）和暗区域（40DR / 46DC，40IR / 56DC，60DR / 66DC或76DR / 80DR / 80DC）覆盖板并横向围绕每个发光区域。 在一个方面，黑暗区域形成有（a）在一个方向上延伸的多个第一条带（40DR，40IR，60DR或76DR）和（b）在另一个方向上延伸的多个第二条带（46DC，56DC，66DC或80DC） 方向并且还比第一条带更远离板延伸。 在另一方面，暗区域包含梯形异形带（86），每个具有形状像直立梯形的宽度轮廓。