公开(公告)号：US20150004793A1

公开(公告)日：2015-01-01

申请号：US14491531

申请日：2014-09-19

Applicant: Lam Research Corporation

Inventor： Rajinder Dhindsa ,  Alexei Marakhatnov ,  Andrew D. Bailey, III

IPC: H01L21/3065 ,  H01L21/31

CPC classification number: H01L21/3065 ,  C23C16/4412 ,  C23C16/45565 ,  C23C16/45574 ,  C23C16/45576 ,  C23C16/50 ,  H01J37/32091 ,  H01J37/32449 ,  H01J37/32834 ,  H01L21/31

Abstract: An electrode is exposed to a plasma generation volume and is defined to transmit radiofrequency power to the plasma generation volume, and includes an upper surface for holding a substrate in exposure to the plasma generation volume. A gas distribution unit is disposed above the plasma generation volume and in a substantially parallel orientation to the electrode. The gas distribution unit includes an arrangement of gas supply ports for directing an input flow of a plasma process gas into the plasma generation volume in a direction substantially perpendicular to the upper surface of the electrode. The gas distribution unit also includes an arrangement of through-holes that each extend through the gas distribution unit to fluidly connect the plasma generation volume to an exhaust region. Each of the through-holes directs an exhaust flow from the plasma generation volume in a direction substantially perpendicular to the upper surface of the electrode.

Abstract translation: 电极暴露于等离子体产生体积，并且被定义为将射频功率传递到等离子体产生体积，并且包括用于保持衬底暴露于等离子体产生体积的上表面。 气体分配单元设置在等离子体产生体积之上并且基本上平行于电极的取向。 气体分配单元包括用于将等离子体处理气体的输入流沿基本上垂直于电极的上表面的方向引导到等离子体产生体积中的气体供给端口的布置。 气体分配单元还包括通孔的布置，每个通孔延伸穿过气体分配单元以将等离子体产生体积流体连接到排气区域。 每个通孔在基本上垂直于电极的上表面的方向上引导来自等离子体产生体积的排气流。

公开(公告)号：US20140174661A1

公开(公告)日：2014-06-26

申请号：US14189978

申请日：2014-02-25

Applicant: Lam Research Corporation

Inventor： Yunsang Kim ,  Andrew D. Bailey, III

IPC: H01J37/32

CPC classification number: H01J37/32385 ,  H01J37/321 ,  H01J37/32366 ,  H01J37/32706 ,  H01L21/02087 ,  H01L21/67069 ,  H01L21/6715

Abstract: A process chamber includes a wafer support to mount a wafer to be processed in the process chamber, with the wafer having an annular edge exclusion area. A first electrically grounded ring extends in an annular path radially outward of the edge exclusion area and is electrically isolated from the wafer support. A second electrode is configured with a center area opposite to the wafer support. A second electrically grounded ring extends in an annular path radially outward of the second electrode and the edge exclusion area. The second electrically grounded ring is electrically isolated from the center area. An annular mount section has a DC bias ring, and the DC bias ring opposes the edge exclusion area when the wafer is present. A DC control circuit is provided for applying a DC voltage to the DC bias ring.

Abstract translation: 处理室包括晶片支撑件，用于将待处理的晶片安装在处理室中，晶片具有环形边缘排除区域。 第一电接地环在边缘排除区域的径向外侧的环形路径中延伸并且与晶片支撑件电隔离。 第二电极配置有与晶片支撑件相对的中心区域。 第二电接地环在第二电极和边缘排除区域的径向外侧的环形路径中延伸。 第二电接地环与中心区电气隔离。 环形安装部分具有DC偏置环，并且当存在晶片时，DC偏置环与边缘排除区域相对。 提供DC控制电路以向DC偏置环施加DC电压。

公开(公告)号：US20130233490A1

公开(公告)日：2013-09-12

申请号：US13870917

申请日：2013-04-25

Applicant: LAM RESEARCH CORPORATION

Inventor： Andrew D. Bailey, III ,  Yunsang Kim

IPC: H01L21/67

CPC classification number: H01J37/32385 ,  H01J37/321 ,  H01J37/32366 ,  H01J37/32706 ,  H01L21/02087 ,  H01L21/67069 ,  H01L21/6715

Abstract: A process chamber includes a wafer support to mount a wafer to be processed in the process chamber, with the wafer having an annular edge exclusion area. A first electrically grounded ring extends in an annular path radially outward of the edge exclusion area and is electrically isolated from the wafer support. A second electrode is configured with a center area opposite to the wafer support. A second electrically grounded ring extends in an annular path radially outward of the second electrode and the edge exclusion area. The second electrically grounded ring is electrically isolated from the center area. An annular mount section has a DC bias ring, and the DC bias ring opposes the edge exclusion area when the wafer is present. A DC control circuit is provided for applying a DC voltage to the DC bias ring.

Abstract translation: 处理室包括晶片支撑件，用于将待处理的晶片安装在处理室中，晶片具有环形边缘排除区域。 第一电接地环在边缘排除区域的径向外侧的环形路径中延伸并且与晶片支撑件电隔离。 第二电极配置有与晶片支撑件相对的中心区域。 第二电接地环在第二电极和边缘排除区域的径向外侧的环形路径中延伸。 第二电接地环与中心区电气隔离。 环形安装部分具有DC偏置环，并且当存在晶片时，DC偏置环与边缘排除区域相对。 提供DC控制电路以向DC偏置环施加DC电压。