公开(公告)号：US10714345B2

公开(公告)日：2020-07-14

申请号：US16578985

申请日：2019-09-23

Applicant: Lam Research Corporation

Inventor： Yunsang Kim ,  Hyuk-Jun Kwon

IPC: H01L21/223 ,  H01L29/167 ,  H01L21/324 ,  H01L21/67 ,  H01L37/00 ,  H01L21/02

Abstract: A method for forming a junction in a germanium (Ge) layer of a substrate includes arranging the substrate in a processing chamber. The method includes performing a plasma pretreatment on the substrate in the processing chamber for a predetermined pretreatment period using a pretreatment plasma gas mixture including hydrogen gas species. The method includes supplying a doping plasma gas mixture to the processing chamber including a phosphorous (P) gas species and an antimony (Sb) gas species. The method includes striking plasma in the processing chamber for a predetermined doping period. The method includes annealing the substrate during a predetermined annealing period to form the junction in the germanium (Ge) layer.

公开(公告)号：US20170256393A1

公开(公告)日：2017-09-07

申请号：US15598166

申请日：2017-05-17

Applicant: Lam Research Corporation

Inventor： Keechan Kim ,  Jack Chen ,  Yunsang Kim ,  Kenneth George Delfin

IPC: H01L21/28 ,  H01L21/67 ,  H01J37/32 ,  H01L21/02

CPC classification number: H01L21/02057 ,  H01J37/32091 ,  H01J37/32385 ,  H01J37/32403 ,  H01L21/02087 ,  H01L21/0209 ,  H01L21/67028

Abstract: A lower electrode plate receives radiofrequency power. A first upper plate is positioned parallel to and spaced apart from the lower electrode plate. A grounded second upper plate is positioned next to the first upper plate. A dielectric support provides support of a workpiece within a region between the lower electrode plate and the first upper plate. A purge gas is supplied at a central location of the first upper plate. A process gas is supplied to a periphery of the first upper plate. The dielectric support positions the workpiece proximate and parallel to the first upper plate, such that the purge gas flows over a top surface of the workpiece so as to prevent the process gas from flowing over the top surface of the workpiece, and so as to cause the process gas to flow around a peripheral edge of the workpiece and below the workpiece.

公开(公告)号：US10068981B2

公开(公告)日：2018-09-04

申请号：US15059208

申请日：2016-03-02

Applicant: Lam Research Corporation

Inventor： Yunsang Kim ,  Reza Arghavani

IPC: H01L21/324 ,  H01L29/66 ,  H01L21/225 ,  H01L29/45 ,  H01L21/285 ,  H01L21/288

Abstract: Methods of doping semiconductor substrates using deposition of a rare earth metal-containing film such as an yttrium-containing film, and annealing techniques are provided herein. Rare earth metal-containing films are deposited using gas, liquid, or solid precursors without a bias and may be deposited conformally. Some embodiments may involve deposition using a plasma. Substrates may be annealed at temperatures less than about 500° C.

公开(公告)号：US20170256622A1

公开(公告)日：2017-09-07

申请号：US15059208

申请日：2016-03-02

Applicant: Lam Research Corporation

Inventor： Yunsang Kim ,  Reza Arghavani

IPC: H01L29/45 ,  H01L21/288 ,  H01L29/66 ,  H01L21/285 ,  H01L21/324 ,  H01L21/225

CPC classification number: H01L29/45 ,  H01L21/2252 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/288 ,  H01L21/324 ,  H01L29/41725 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/78

Abstract: Methods of doping semiconductor substrates using deposition of a rare earth metal-containing film such as an yttrium-containing film, and annealing techniques are provided herein. Rare earth metal-containing films are deposited using gas, liquid, or solid precursors without a bias and may be deposited conformally. Some embodiments may involve deposition using a plasma. Substrates may be annealed at temperatures less than about 500° C.

公开(公告)号：US09543150B2

公开(公告)日：2017-01-10

申请号：US14735541

申请日：2015-06-10

Applicant: LAM RESEARCH CORPORATION

Inventor： Yunsang Kim ,  YounGi Hong ,  Ivan Berry

IPC: H01L21/265 ,  H01L21/225 ,  H01L21/30 ,  H01L21/324 ,  H01L21/02

CPC classification number: H01L21/02041 ,  H01L21/2236 ,  H01L21/2658

Abstract: A method for forming a junction on a substrate includes removing a native oxide layer of a bulk material; doping an outer layer of the bulk material with molecular hydrogen to create a hydrogen-doped outer layer; and nano-doping the hydrogen-doped outer layer using one of boron or phosphorous to a target junction depth to create a nano-doped layer.

Abstract translation: 在基板上形成结的方法包括：去除本体材料的天然氧化物层; 用分子氢掺杂本体材料的外层以产生掺杂氢的外层; 并且使用硼或磷中的一种将目标结深度纳入掺杂氢的外层以产生纳米掺杂层。

公开(公告)号：US20160365251A1

公开(公告)日：2016-12-15

申请号：US14735541

申请日：2015-06-10

Applicant: LAM RESEARCH CORPORATION

Inventor： Yunsang Kim ,  YounGi Hong ,  Ivan Berry

IPC: H01L21/225 ,  H01L21/324 ,  H01L21/30

CPC classification number: H01L21/02041 ,  H01L21/2236 ,  H01L21/2658

Abstract: A method for forming a junction on a substrate includes removing a native oxide layer of a bulk material; doping an outer layer of the bulk material with molecular hydrogen to create a hydrogen-doped outer layer; and nano-doping the hydrogen-doped outer layer using one of boron or phosphorous to a target junction depth to create a nano-doped layer.

Abstract translation: 在基板上形成结的方法包括：去除本体材料的天然氧化物层; 用分子氢掺杂本体材料的外层以产生掺杂氢的外层; 并且使用硼或磷中的一种将目标结深度纳入掺杂氢的外层以产生纳米掺杂层。

公开(公告)号：US20140051255A1

公开(公告)日：2014-02-20

申请号：US14065018

申请日：2013-10-28

Applicant: Lam Research Corporation

Inventor： Tong Fang ,  Yunsang Kim ,  Andre D. Bailey, III ,  Olivier Rigoutat ,  George Stojakovic

IPC: H01L21/3065

CPC classification number: H01L21/3065 ,  H01J37/32366 ,  H01L21/02068 ,  H01L21/02087 ,  H01L21/32136 ,  H01L21/6708

Abstract: A method of bevel edge etching a semiconductor substrate having exposed copper surfaces with a fluorine-containing plasma in a bevel etcher in which the semiconductor substrate is supported on a semiconductor substrate support comprises bevel edge etching the semiconductor substrate with the fluorine-containing plasma in the bevel etcher; evacuating the bevel etcher after the bevel edge etching is completed; flowing defluorinating gas into the bevel etcher; energizing the defluorinating gas into a defluorination plasma at a periphery of the semiconductor substrate; and processing the semiconductor substrate with the defluorination plasma under conditions to prevent discoloration of the exposed copper surfaces of the semiconductor substrate upon exposure, the discoloration occurring upon prolonged exposure to air.

Abstract translation: 在半导体衬底支撑在半导体衬底支撑体上的斜面蚀刻器中，使用具有含氟等离子体的具有暴露的铜表面的半导体衬底进行斜边蚀刻的方法包括：在半导体衬底支撑体中的含氟等离子体 斜角蚀刻机 在斜边蚀刻完成之后排空斜面蚀刻机; 将脱氟气体流入斜面蚀刻机; 在所述半导体衬底的外围将所述脱氟气体通电为脱氟等离子体; 并且在曝光时防止半导体衬底的暴露的铜表面的变色的条件下，用脱氟等离子体处理半导体衬底，在长时间暴露于空气时发生变色。

公开(公告)号：US10811282B2

公开(公告)日：2020-10-20

申请号：US15638313

申请日：2017-06-29

Applicant: Lam Research Corporation

Inventor： Tong Fang ,  Yunsang Kim ,  Keechan Kim ,  George Stojakovic

IPC: H01L21/00 ,  H01L21/67 ,  H01J37/32 ,  H01L21/02 ,  H01L21/3065

Abstract: An upper plasma-exclusion-zone ring for a bevel etcher is provided that is configured to etch a bevel edge of a substrate. The upper plasma-exclusion-zone ring includes a ring-shaped body and a radially-inner stepped surface. The ring-shaped body of the upper plasma-exclusion-zone ring defines an upper surface, a lower surface, a radially inner surface, and a radially outer surface. The radially-inner stepped surface of the upper plasma-exclusion-zone ring extends inwardly into the ring-shaped body between the radially inner surface of the ring-shaped body and the lower surface of the ring-shaped body. The ring-shaped body is made of a material selected from a group consisting of aluminum oxide, aluminum nitride, silicon, silicon carbide, silicon nitride, and yttria.

公开(公告)号：US10748747B2

公开(公告)日：2020-08-18

申请号：US15724177

申请日：2017-10-03

Applicant: Lam Research Corporation

Inventor： Keechan Kim ,  Yunsang Kim

IPC: H01J37/32 ,  B08B7/00

Abstract: A system for controlling a size of an edge exclusion region is described. The system includes an upper electrode, an upper plasma exclusion zone (PEZ) ring located beside the upper electrode, an upper electrode extension located beside the upper PEZ ring, and a system controller configured to generate signals regarding a first position and a second position of the upper PEZ ring. The system further includes an actuator and a position controller coupled to the system controller and the actuator. The position controller is configured to receive the signals from the system controller, and to control the actuator based on the signals to achieve the first position and the second position The first and second positions are achieved independent of any movement of the upper electrode.

公开(公告)号：US09881788B2

公开(公告)日：2018-01-30

申请号：US14285544

申请日：2014-05-22

Applicant: Lam Research Corporation

Inventor： Yunsang Kim ,  Kaushik Chattopadhyay ,  Gregory Sexton ,  Youn Gi Hong

IPC: H01L21/00 ,  H01J37/00 ,  H01L21/02 ,  H01L27/115 ,  C23C16/52 ,  H01L21/67 ,  C23C16/458 ,  C23C16/02 ,  C23C16/44 ,  H01J37/32

CPC classification number: H01L21/02271 ,  C23C16/02 ,  C23C16/04 ,  C23C16/44 ,  C23C16/4401 ,  C23C16/455 ,  C23C16/45519 ,  C23C16/458 ,  C23C16/52 ,  H01J37/32082 ,  H01J37/32403 ,  H01J37/32715 ,  H01L21/02301 ,  H01L21/02315 ,  H01L21/02345 ,  H01L21/67069 ,  H01L21/67207 ,  H01L27/115

Abstract: The embodiments disclosed herein pertain to methods and apparatus for depositing stress compensating layers and sacrificial layers on either the front side or back side of a substrate. In various implementations, back side deposition occurs while the wafer is in a normal front side up orientation. The front/back side deposition may be performed to reduce stress introduced through deposition on the front side of the wafer. The back side deposition may also be performed to minimize back side particle-related problems that occur during post-deposition processing such as photolithography.