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公开(公告)号：US20080073749A1
公开(公告)日：2008-03-27
申请号：US11949569
申请日：2007-12-03
IPC分类号： H01L29/00
CPC分类号： H01L23/5252 , G11C17/165 , G11C2229/763 , H01L27/11206 , H01L2924/0002 , H01L2924/3011 , Y10S257/928 , H01L2924/00
摘要： The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming.
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82.发明申请Methods and Apparatus for Characterizing Electronic Fuses Used to Personalize an Integrated Circuit 失效用于表征用于个性化集成电路的电子保险丝的方法和装置公开(公告)号：US20080048761A1
公开(公告)日：2008-02-28
申请号：US11923916
申请日：2007-10-25
IPC分类号： H01H37/76
CPC分类号： G01R31/31853 , G01R31/30 , G01R31/3004
摘要： An integrated circuit device having at least one fuse capable of being blown in order to provide measurements of fuse current-voltage characteristics is provided. The integrated circuit device also provides at least one pulse generation circuit associated with the fuse and capable of generating a pulse to blow the fuse through one or more DC input signals.
摘要翻译： 提供一种具有至少一个能够被熔断以便提供熔丝电流 - 电压特性测量的熔断器的集成电路器件。 集成电路装置还提供与熔丝相关联的至少一个脉冲发生电路，并且能够产生脉冲以通过一个或多个DC输入信号来熔断熔丝。
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83.发明申请ELECTRICAL FUSES COMPRISING THIN FILM TRANSISTORS (TFTS), AND METHODS FOR PROGRAMMING SAME 有权包含薄膜晶体管（TFTS）的电熔丝及其编程方法公开(公告)号：US20070158781A1
公开(公告)日：2007-07-12
申请号：US11306597
申请日：2006-01-04
IPC分类号： H01L29/00
CPC分类号： H01L29/42384 , H01L23/345 , H01L23/5256 , H01L29/78669 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to electrical fuses that each comprises at least one thin film transistor. In one embodiment, the electrical fuse of the present invention comprises a hydrogenated thin film transistor with an adjacent heating element. Programming of such an electrical fuse can be effectuated by heating the hydrogenated thin film transistor so as to cause at least partial dehydrogenation. Consequentially, the thin film transistor exhibits detectible physical property change(s), which defines a programmed state. In an alternative embodiment of the present invention, the electrical fuse comprises a thin film transistor that is either hydrogenated or not hydrogenated. Programming of such an alternative electrical fuse can be effectuated by applying a sufficient high back gate voltage to the thin film transistor to cause state changes in the channel-gate interface. In this manner, the thin film transistor also exhibits detectible property change(s) to define a programmed state.
摘要翻译： 本发明涉及电熔丝，每个电熔丝包括至少一个薄膜晶体管。 在一个实施例中，本发明的电熔丝包括具有相邻加热元件的氢化薄膜晶体管。 可以通过加热氢化薄膜晶体管来实现这种电熔丝的编程，从而至少部分脱氢。 因此，薄膜晶体管表现出可检测的物理特性变化，其定义了编程状态。 在本发明的替代实施例中，电熔丝包括被氢化或未氢化的薄膜晶体管。 可以通过向薄膜晶体管施加足够的高背栅电压来引起通道栅极界面的状态变化来实现这种替代电熔丝的编程。 以这种方式，薄膜晶体管还具有可检测的特性变化以限定编程状态。
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公开(公告)号：US20060278932A1
公开(公告)日：2006-12-14
申请号：US11160151
申请日：2005-06-10
IPC分类号： H01L29/94
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The present invention provides electrically-programmable fuse structures having radiation inhibitive properties for preventing non-destructive security breaches by radiation imaging techniques such as X-ray imaging, without adversely effecting fuse programmability, and methods of designing the same.
摘要翻译： 本发明提供了具有辐射抑制特性的电可编程熔丝结构，用于通过诸如X射线成像的放射线成像技术来防止非破坏性的安全漏洞，而不会对保险丝可编程性产生不利影响，以及设计熔丝可编程性的方法。
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公开(公告)号：US20060278895A1
公开(公告)日：2006-12-14
申请号：US11152750
申请日：2005-06-14
申请人： Geoffrey Burr , Chandrasekharan Kothandaraman , Chung Lam , Xiao Liu , Stephen Rossnagel , Christy Tyberg , Robert Wisnieff
发明人： Geoffrey Burr , Chandrasekharan Kothandaraman , Chung Lam , Xiao Liu , Stephen Rossnagel , Christy Tyberg , Robert Wisnieff
CPC分类号： H01L23/5256 , H01L23/5252 , H01L45/06 , H01L45/1206 , H01L45/1226 , H01L45/1286 , H01L45/1293 , H01L45/144 , H01L45/148 , H01L45/1683 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed through the fuse cell in order to change the material from a less resistive material to a more resistive material through heating the phase change material in the crystalline state to the melting point then quickly quenching the material into the amorphous state. The reversible programming is achieved by passing a lower current through the fuse cell to convert the high resistivity amorphous material to a lower resistivity crystalline material. Appropriate sense-circuitry is integrated to read the information stored in the fuses, wherein said sense circuitry is used to enable or disable circuitry.
摘要翻译： 集成电路中的可逆熔丝结构通过实现具有短路相变材料的熔断电池获得，所述相变材料与能够使电流通过相变材料线（熔丝电池）的通孔和线结构相接触。 电流通过熔丝电池，以便通过将结晶状态的相变材料加热至熔点，从而将材料从较小电阻的材料转变为更电阻的材料，然后快速将材料淬火成非晶状态。 可逆编程通过使较低电流通过熔丝电池来实现，以将高电阻率无定形材料转换成较低电阻率的晶体材料。 集成适当的感测电路以读取存储在熔丝中的信息，其中所述感测电路用于启用或禁用电路。
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公开(公告)号：US07042094B2
公开(公告)日：2006-05-09
申请号：US10771000
申请日：2004-02-02
CPC分类号： H01L24/02 , H01L23/5226 , H01L2224/04042 , H01L2924/01013 , H01L2924/01014 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/14
摘要： A multi-level via structure for a semiconductor chip in which the collective area of a vias structure is not entirely oriented directly in-line with the collective area of an adjacent vias structure. In one embodiment, adjacent via structure areas appear to be crisscrossed in relation to one another and in another embodiment adjacent via structure areas do not coincide at all from a perpendicular perspective.
摘要翻译： 一种用于半导体芯片的多电平通孔结构，其中通孔结构的集合区域不完全定向成与邻近的通孔结构的集体区域成直线。 在一个实施例中，相邻的通孔结构区域看起来相对于彼此十字交叉，并且在另一个实施例中，相邻的通孔结构区域根本不与垂直的透视重合。
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公开(公告)号：US07029955B2
公开(公告)日：2006-04-18
申请号：US10669026
申请日：2003-09-23
IPC分类号： H01L21/82
CPC分类号： H01L23/5329 , H01L23/5222 , H01L23/5256 , H01L23/5258 , H01L23/66 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A silicided polysilicon based fuse device that is programmable by optical and electrical energy in the polysilicon layer without damage to nearby structures, comprising: a Si substrate; an insulating layer disposed on the substrate; and a fuse device section comprising poly-Si/a silicide/ and a barrier layer, the fuse device section forming an electrical discontinuity in the poly Si layer in response to an electrical pulse or an optical pulse applied to it.
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公开(公告)号：US06617914B1
公开(公告)日：2003-09-09
申请号：US10092114
申请日：2002-03-05
IPC分类号： G11C1134
摘要： An antifuse having a dielectric disposed between a plurality of conductive elements is programmed with one of the conductive elements connected to a capacitor. The antifuse is programmed to an “on” state by precharging the capacitor and then applying a programming voltage to another one of the conductive elements. This results in the breakdown of the interposed dielectric to form a conductive link between the conductive elements. Immediately, following the formation of a conductive link, the electrical energy stored in the capacitor is released through the conductive link across the dielectric. Further, the capacitor can be common to a plurality of programmable antifuses and the application of the programming voltage serves to select one of the plurality of antifuses to be ‘blown’. This arrangement can be realized in a FET and the device can be easily integrated in the CMOS process commonly used for the manufacture of memory arrays and logic circuitry.
摘要翻译： 具有设置在多个导电元件之间的电介质的反熔丝被编程为连接到电容器的导电元件之一。 通过对电容器进行预充电，然后将编程电压施加到另一个导电元件，将反熔丝编程为“导通”状态。 这导致插入的电介质的击穿以在导电元件之间形成导电连接。 紧随着形成导电连接，存储在电容器中的电能通过电介质上的导电链路释放。 此外，电容器对于多个可编程反熔丝可以是共同的，并且编程电压的应用用于选择要被“吹制”的多个反熔丝中的一个，这种布置可以在FET中实现，并且该器件可以容易地集成 在通常用于制造存储器阵列和逻辑电路的CMOS工艺中。
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89.发明授权Secure anti-fuse with low voltage programming through localized diffusion heating 失效通过局部扩散加热，通过低电压编程实现安全的反熔丝公开(公告)号：US08569755B2
公开(公告)日：2013-10-29
申请号：US13612938
申请日：2012-09-13
IPC分类号： H01L29/04
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An antifuse has first and second semiconductor regions having one conductivity type and a third semiconductor region therebetween having an opposite conductivity type. A conductive region contacting the first region has a long dimension in a second direction transverse to the direction of a long dimension of a gate. An antifuse anode is spaced apart from the first region in the second direction and a contact is connected with the second region. Applying a programming voltage between the anode and the contact with gate bias sufficient to fully turn on field effect transistor operation of the antifuse heats the first region to drive a dopant outwardly, causing an edge of the first region to move closer to an edge of the second region and reduce electrical resistance between the first and second regions by an one or more orders of magnitude.
摘要翻译： 反熔丝具有一个导电类型的第一和第二半导体区域和它们之间具有相反导电类型的第三半导体区域。 接触第一区域的导电区域在横向于栅极的长尺寸方向的第二方向上具有长尺寸。 反熔丝阳极在第二方向上与第一区域间隔开，并且触点与第二区域连接。 在阳极和接触之间施加编程电压，栅极偏压足以完全导通反熔丝的场效应晶体管操作加热第一区域以向外驱动掺杂剂，导致第一区域的边缘更接近于 并且将第一和第二区域之间的电阻降低一个或多个数量级。
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公开(公告)号：US20120184073A1
公开(公告)日：2012-07-19
申请号：US13433423
申请日：2012-03-29
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L21/28282 , H01L21/823462 , H01L21/823468 , H01L27/1052 , H01L27/11573 , H01L29/4234 , H01L29/4983 , H01L29/517 , H01L29/6659 , H01L29/66833 , H01L29/792
摘要： A method of fabricating a memory device is provided that may begin with forming a layered gate stack atop a semiconductor substrate and patterning a metal electrode layer stopping on the high-k gate dielectric layer of the layered gate stack to provide a first metal gate electrode and a second metal gate electrode on the semiconductor substrate. In a next process sequence, at least one spacer is formed on the first metal gate electrode atop a portion of the high-k gate dielectric layer, wherein a remaining portion of the high-k gate dielectric is exposed. The remaining portion of the high-k gate dielectric layer is etched to provide a first high-k gate dielectric having a portion that extends beyond a sidewall of the first metal gate electrode and a second high-k gate dielectric having an edge that is aligned to a sidewall of the second metal gate electrode.
摘要翻译： 提供一种制造存储器件的方法，其可以开始于在半导体衬底顶上形成分层栅极堆叠并且图案化停止在层状栅叠层的高k栅极电介质层上的金属电极层，以提供第一金属栅电极和 半导体衬底上的第二金属栅电极。 在下一个处理顺序中，在第一金属栅电极的高k栅介质层的一部分顶上形成至少一个间隔物，其中高k栅极电介质的剩余部分被暴露。 蚀刻高k栅极电介质层的剩余部分以提供具有延伸超过第一金属栅电极的侧壁的部分的第一高k栅极电介质和具有对准边缘的第二高k栅极电介质 到第二金属栅电极的侧壁。
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