公开(公告)号：US11960985B2

公开(公告)日：2024-04-16

申请号：US17940845

申请日：2022-09-08

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale

IPC: G06N3/063 ,  H04N23/617 ,  H04N25/709 ,  H04N25/75 ,  H04N25/771 ,  H04N25/79

CPC classification number: G06N3/063 ,  H04N23/617 ,  H04N25/709 ,  H04N25/75 ,  H04N25/771 ,  H04N25/79

Abstract: A method of artificial neural network computations, including: receiving image data having pixel values; generating, from the pixel values, a column of inputs to a set of artificial neurons; identifying a region of memory cells of the integrated circuit device having threshold voltages programmed to represent a weight matrix for the set of artificial neurons; instructing voltage drivers in the integrated circuit device to apply voltages to the region of memory cells according to the column of inputs; obtaining, based on the region of memory cells responsive to the applied voltages, a first column of data from an operation of multiplication and accumulation applied on the weight matrix and the column of inputs; and applying activation functions of the set of artificial neurons to the first column of data to generate a second column of data representative of outputs of the set of artificial neuron.

公开(公告)号：US20240104897A1

公开(公告)日：2024-03-28

申请号：US17953042

申请日：2022-09-26

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Saideep Tiku ,  Robert Noel Bielby

IPC: G06V10/77 ,  B60R1/12 ,  B60R1/22 ,  G01S7/48 ,  G01S17/08 ,  G01S17/89 ,  G06V10/20 ,  G06V10/60 ,  G06V20/40 ,  G06V20/58 ,  H04N7/18

CPC classification number: G06V10/77 ,  B60R1/12 ,  B60R1/22 ,  G01S7/4808 ,  G01S17/08 ,  G01S17/89 ,  G06V10/20 ,  G06V10/60 ,  G06V20/41 ,  G06V20/58 ,  H04N7/183 ,  B60R2001/1253 ,  B60R2300/105 ,  B60R2300/30 ,  G06V2201/08

Abstract: Methods, systems, and devices for video stream augmentation using a deep learning device are described. A machine learning device of a vehicle may augment a video stream received from cameras of the vehicle and may output the augmented video stream to a display component of the vehicle. For example, a camera of the vehicle may record a video stream of and a sensor of the vehicle may detect information about an environment associated with the vehicle. The camera and sensor may transmit the video stream and information, respectively, to the machine learning device, which may process and modify the video stream based on parameters of the video stream and/or the information. The machine learning device may transmit the modified video streams to the display component, and the display component may display aspects of the modified video stream on a display of the vehicle, such as a rearview mirror.

公开(公告)号：US11942135B2

公开(公告)日：2024-03-26

申请号：US17729830

申请日：2022-04-26

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Jaime Cummins

IPC: G11C11/34 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06N3/063 ,  H04N23/69 ,  H04N23/80

CPC classification number: G11C11/34 ,  G06F9/30007 ,  G06F9/3893 ,  G06F9/5027 ,  G06N3/063 ,  H04N23/69 ,  H04N23/80

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An integrated circuit may be configured to execute instructions with matrix operands and configured with: random access memory configured to store instructions executable by the Deep Learning Accelerator and store matrices of an Artificial Neural Network; a connection between the random access memory and the Deep Learning Accelerator; a first interface to a memory controller of a Central Processing Unit; and a second interface to an image generator, such as a camera. While the Deep Learning Accelerator is using the random access memory to process current input to the Artificial Neural Network in generating current output from the Artificial Neural Network, the Deep Learning Accelerator may concurrently load next input from the camera into the random access memory; and at the same time, the Central Processing Unit may concurrently retrieve prior output from the random access memory.

公开(公告)号：US20240089634A1

公开(公告)日：2024-03-14

申请号：US17940955

申请日：2022-09-08

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale

IPC: H04N5/3745 ,  G06N3/08 ,  G06V10/764 ,  G06V10/82 ,  G06V10/94 ,  G11C7/10 ,  G11C11/54

CPC classification number: H04N5/37452 ,  G06N3/08 ,  G06V10/764 ,  G06V10/82 ,  G06V10/945 ,  G11C7/1096 ,  G11C11/54 ,  G06V2201/10

Abstract: A method for a digital camera adaptable to monitor a scene to detect a condition of interest to a user. The digital camera can program, in a first mode, first memory cells according to first weight matrices to classify images captured by the digital camera. Second memory cells are programmed in a second mode to store data representative of the images. The digital camera can perform operations of multiplication and accumulation using the first memory cells to compute first classifications of the images. In response to mismatches between the first classifications and second classifications identified by the user for the images, the digital camera can execute instructions to determine second weight matrices and program, in the first mode, third memory cells, according to the second weight matrices for improved capability in detecting the condition represented by image classifications in a predetermined category.

公开(公告)号：US20240087653A1

公开(公告)日：2024-03-14

申请号：US17940945

申请日：2022-09-08

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale

IPC: G11C16/12 ,  G06F7/544 ,  G11C16/24 ,  G11C16/26

CPC classification number: G11C16/12 ,  G06F7/5443 ,  G11C16/24 ,  G11C16/26

Abstract: An integrated circuit device having a mechanism to check calibration of memory cells configured to perform operations of multiplication and accumulation. The integrated circuit device programs, in a first mode, threshold voltages of first memory cells in a memory cell array to store weight data, and programs, in a second mode, threshold voltages of second memory cells in the memory cell array to store a first result of applying an operation of multiplication and accumulation to a sample input and the weight data. During a calibration check, the integrated circuit device performs the operation using the first memory cells to obtain a second result, and compares the first result, retrieved from the second memory cells, and the second result to determine whether calibration of output current characteristics of the first memory cells programmed in the first mode is corrupted.

公开(公告)号：US20240086691A1

公开(公告)日：2024-03-14

申请号：US17940845

申请日：2022-09-08

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale

IPC: H04N5/3745 ,  G06N3/063 ,  H04N5/369 ,  H04N5/378

CPC classification number: H04N5/37452 ,  G06N3/063 ,  H04N5/3698 ,  H04N5/378 ,  H04N5/379

Abstract: A method of artificial neural network computations, including: receiving image data having pixel values; generating, from the pixel values, a column of inputs to a set of artificial neurons; identifying a region of memory cells of the integrated circuit device having threshold voltages programmed to represent a weight matrix for the set of artificial neurons; instructing voltage drivers in the integrated circuit device to apply voltages to the region of memory cells according to the column of inputs; obtaining, based on the region of memory cells responsive to the applied voltages, a first column of data from an operation of multiplication and accumulation applied on the weight matrix and the column of inputs; and applying activation functions of the set of artificial neurons to the first column of data to generate a second column of data representative of outputs of the set of artificial neuron.

公开(公告)号：US11887647B2

公开(公告)日：2024-01-30

申请号：US16844993

申请日：2020-04-09

Applicant: Micron Technology, Inc.

Inventor： Poorna Kale ,  Jaime Cummins

IPC: G06F9/38 ,  G11C11/34 ,  G06F9/30 ,  G06N3/063 ,  G06F9/50 ,  G06N3/10 ,  G06F17/16

CPC classification number: G11C11/34 ,  G06F9/30007 ,  G06F9/3877 ,  G06F9/3893 ,  G06F9/5027 ,  G06F17/16 ,  G06N3/063 ,  G06N3/10

Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An integrated circuit may be configured to execute instructions with matrix operands and configured with: random access memory configured to store instructions executable by the Deep Learning Accelerator and store matrices of an Artificial Neural Network; a connection between the random access memory and the Deep Learning Accelerator; a first interface to a memory controller of a Central Processing Unit; and a second interface to a direct memory access controller. While the Deep Learning Accelerator is using the random access memory to process current input to the Artificial Neural Network in generating current output from the Artificial Neural Network, the direct memory access controller may concurrently load next input into the random access memory; and at the same time, the Central Processing Unit may concurrently retrieve prior output from the random access memory.

公开(公告)号：US11816265B1

公开(公告)日：2023-11-14

申请号：US17823787

申请日：2022-08-31

Applicant: Micron Technology, Inc.

Inventor： Saideep Tiku ,  Poorna Kale

IPC: G06F3/01

CPC classification number: G06F3/015 ,  G06F2203/011

Abstract: In some implementations, an extended reality (XR) device may generate a first event in a virtual environment, wherein the first event is associated with a first difficulty level. The XR device may detect vital information of a user associated with the XR device, wherein the vital information is associated with the first event. The XR device may determine whether the vital information satisfies a threshold. The XR device may transmit, to a server, an indication that indicates whether the vital information satisfies the threshold. The XR device may receive, from the server, virtual environment information, wherein the virtual environment information is based on whether the vital information satisfies the threshold. The XR device may generate, based on the virtual environment information, a second event in the virtual environment, wherein the second event is associated with a second difficulty level.

公开(公告)号：US11775816B2

公开(公告)日：2023-10-03

申请号：US16538078

申请日：2019-08-12

Applicant: Micron Technology, Inc.

Inventor： Robert Richard Noel Bielby ,  Poorna Kale

IPC: G06F12/00 ,  G06N3/08 ,  G06N5/04 ,  G06N3/049 ,  G06F3/06 ,  G06F12/02

CPC classification number: G06N3/08 ,  G06F3/0605 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/0238 ,  G06N3/049 ,  G06N5/04 ,  G06F2212/251

Abstract: Systems, methods and apparatus of optimizing neural network computations of predictive maintenance of vehicles. For example, a data storage device of a vehicle includes: a host interface configured to receive a sensor data stream from at least one sensor configured on the vehicle; at least one storage media component having a non-volatile memory; and a controller. The non-volatile memory is configured into multiple partitions (e.g., namespaces) having different sets of memory operation settings configured for different types of data related to an artificial neural network (ANN). The partitions include an output partition configured to store output data from the ANN. The sensor data stream is applied in the ANN to predict a maintenance service of the vehicle. The memory units of the input partition can be configured for cyclic sequential overwrite of selected outputs that are updated less frequently than inputs to the ANN.

公开(公告)号：US11769076B2

公开(公告)日：2023-09-26

申请号：US16601386

申请日：2019-10-14

Applicant: Micron Technology, Inc.

Inventor： Amit Gattani ,  Poorna Kale

IPC: G06N20/00 ,  G06F13/16 ,  G06F3/06 ,  G06N3/08

CPC classification number: G06N20/00 ,  G06F3/061 ,  G06F3/0659 ,  G06F13/1668 ,  G06N3/08

Abstract: A memory component includes a memory region to store a machine learning model and input data and another memory region to store host data from a host system. A controller can be coupled to the memory component and can include in-memory logic to perform a machine learning operation by applying the machine learning model to the input data to generate an output data. A bus can receive additional data from the host system and a decoder can receive the additional data from the bus and can transmit the additional data to the other memory region or the in-memory logic of the controller based on a characteristic of the additional data.