公开(公告)号：US20210327898A1

公开(公告)日：2021-10-21

申请号：US17328237

申请日：2021-05-24

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Francois H. Fabreguette ,  Richard J. Hill ,  Purnima Narayanan ,  Shyam Surthi

IPC: H01L27/11582 ,  G11C16/08 ,  H01L21/02 ,  H01L27/1157

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have conductive terminal ends within control gate regions. The control gate regions are vertically spaced from one another by first insulative regions which include first insulative material. Charge-storage material is laterally outward of the conductive terminal ends, and is configured as segments. The segments of the charge-storage material are arranged one atop another and are vertically spaced from one another by second insulative regions which include second insulative material. The second insulative material has a different dielectric constant than the first insulative material. Charge-tunneling material extends vertically along the stack, and is adjacent to the segments of the charge-trapping material. Channel material extends vertically along the stack, and is adjacent to the charge-tunneling material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11120852B2

公开(公告)日：2021-09-14

申请号：US16793263

申请日：2020-02-18

Applicant: Micron Technology, Inc.

Inventor： Armin Saeedi Vahdat ,  Richard J. Hill ,  Aaron Michael Lowe

IPC: G11C7/18 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/1157

Abstract: A method used in forming a memory array comprises forming digitlines above and electrically couple to memory cells there-below. The digitlines are laterally-spaced relative one another in a vertical cross-section. An upwardly-open void-space is laterally-between immediately-adjacent of the digitlines in the vertical cross-section. Conductive material of the digitlines is covered with masking material that is in and less-than-fills the upwardly-open void-spaces. The masking material is removed from being directly above tops of the digitlines to expose the conductive digitline material and to leave the masking material over sidewalls of the conductive digitline material in the upwardly-open void-spaces. Insulative material is selectively grown from the exposed conductive digitline material relative to the masking material across the upwardly-open void-spaces to form covered void-spaces there-from between the immediately-adjacent digitlines in the vertical cross-section. Structures independent of method are disclosed.

公开(公告)号：US11081497B2

公开(公告)日：2021-08-03

申请号：US16547885

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Richard J. Hill ,  Byeung Chul Kim ,  Akira Goda

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L29/51 ,  H01L29/792 ,  H01L21/28 ,  H01L29/49 ,  H01L29/788

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and second regions proximate to the control gate regions. High-k dielectric material wraps around ends of the control gate regions, and is not along the second regions. Charge-blocking material is adjacent to the high-k dielectric material. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another by gaps. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.

公开(公告)号：US10937798B2

公开(公告)日：2021-03-02

申请号：US16179572

申请日：2018-11-02

Applicant: Micron Technology, Inc.

Inventor： Changhan Kim ,  Richard J. Hill ,  John D. Hopkins ,  Collin Howder

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11556 ,  H01L21/28

Abstract: A memory array comprises a vertical stack comprising alternating insulative tiers and wordline tiers. The wordline tiers comprise gate regions of individual memory cells. The gate regions individually comprise part of a wordline in individual of the wordline tiers. Channel material extends elevationally through the insulative tiers and the wordline tiers. The individual memory cells comprise a memory structure laterally between the gate region and the channel material. Individual of the wordlines comprise opposing laterally-outer longitudinal edges. The longitudinal edges individually comprise a longitudinally-elongated recess extending laterally into the respective individual wordline. Methods are disclosed.

公开(公告)号：US20210057437A1

公开(公告)日：2021-02-25

申请号：US16548320

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Davide Resnati ,  Paolo Tessariol ,  Richard J. Hill ,  John D. Hopkins

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L29/788 ,  H01L29/792 ,  H01L21/02

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions. High-k dielectric material is adjacent to the control gate regions and is configured as an arrangement of first vertically-extending linear segments which are vertically spaced from one another. Charge-blocking material is adjacent to the high-k dielectric material and is configured as an arrangement of second vertically-extending linear segments which are vertically spaced from one another. Charge-storage material is adjacent to the charge-blocking material and is configured as an arrangement of third vertically-extending linear segments which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies and methods of forming integrated assemblies.

公开(公告)号：US20200373322A1

公开(公告)日：2020-11-26

申请号：US16417162

申请日：2019-05-20

Applicant: Micron Technology, Inc.

Inventor： Shyam Surthi ,  Byeung Chul Kim ,  Richard J. Hill ,  Francois H. Fabreguette ,  Gurtej S. Sandhu

IPC: H01L27/11582 ,  G11C5/06 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. A channel material extends vertically along the stack. The channel material includes a semiconductor composition and has first segments alternating with second segments. The first segments are adjacent the wordline levels and the second segments are adjacent the insulative levels. The first segments have a first dopant distribution and the second segments have a second dopant distribution which is different from the first dopant distribution. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US10777576B1

公开(公告)日：2020-09-15

申请号：US16374527

申请日：2019-04-03

Applicant: Micron Technology, Inc.

Inventor： Byeung Chul Kim ,  Francois H. Fabreguette ,  Richard J. Hill ,  Purnima Narayanan ,  Shyam Surthi

IPC: H01L21/02 ,  H01L27/1157 ,  H01L27/11582 ,  G11C16/08

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. The wordline levels have conductive terminal ends within control gate regions. The control gate regions are vertically spaced from one another by first insulative regions which include first insulative material. Charge-storage material is laterally outward of the conductive terminal ends, and is configured as segments. The segments of the charge-storage material are arranged one atop another and are vertically spaced from one another by second insulative regions which include second insulative material. The second insulative material has a different dielectric constant than the first insulative material. Charge-tunneling material extends vertically along the stack, and is adjacent to the segments of the charge-trapping material. Channel material extends vertically along the stack, and is adjacent to the charge-tunneling material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20200286895A1

公开(公告)日：2020-09-10

申请号：US16809924

申请日：2020-03-05

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Srinivas Pulugurtha ,  Richard J. Hill ,  Yunfei Gao ,  Nicholas R. Tapias ,  Litao Yang ,  Haitao Liu

IPC: H01L27/108

Abstract: Some embodiments include an integrated assembly having digit lines which extend along a first direction, and which are spaced from one another by intervening regions. Each of the intervening regions has a first width along a cross-section. Pillars extend upwardly from the digit lines; and the pillars include transistor channel regions extending vertically between upper and lower source/drain regions. Storage elements are coupled with the upper source/drain regions. Wordlines extend along a second direction which crosses the first direction. The wordlines include gate regions adjacent the channel regions. Shield lines are within the intervening regions and extend along the first direction. The shield lines may be coupled with at least one reference voltage node. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20190267396A1

公开(公告)日：2019-08-29

申请号：US16410973

申请日：2019-05-13

Applicant: Micron Technology, Inc.

Inventor： David Daycock ,  Richard J. Hill ,  Christopher Larsen ,  Woohee Kim ,  Justin B. Dorhout ,  Brett D. Lowe ,  John D. Hopkins ,  Qian Tao ,  Barbara L. Casey

IPC: H01L27/11582 ,  H01L29/10 ,  H01L21/28 ,  H01L29/792 ,  H01L29/423

Abstract: Some embodiments include a memory array which has a vertical stack of alternating insulative levels and wordline levels. The wordline levels have terminal ends corresponding to control gate regions. Charge-trapping material is along the control gate regions of the wordline levels and not along the insulative levels. The charge-trapping material is spaced from the control gate regions by charge-blocking material. Channel material extends vertically along the stack and is laterally spaced from the charge-trapping material by dielectric material. Some embodiments include methods of forming NAND memory arrays.

公开(公告)号：US20190206870A1

公开(公告)日：2019-07-04

申请号：US15898086

申请日：2018-02-15

Applicant: Micron Technology, Inc.

Inventor： Yunfei Gao ,  Richard J. Hill ,  Gurtej S. Sandhu ,  Haitao Liu ,  Deepak Chandra Pandey ,  Srinivas Pulugurtha ,  Kamal M. Karda

IPC: H01L27/108 ,  H01L29/20 ,  H01L29/423

Abstract: A recessed access device comprises a conductive gate in a trench in semiconductor material. A gate insulator is along sidewalls and a base of the trench between the conductive gate and the semiconductor material. A pair of source/drain regions is in upper portions of the semiconductor material on opposing sides of the trench. A channel region is in the semiconductor material below the pair of source/drain regions along the trench sidewalls and around the trench base. At least some of the channel region comprises GaP.