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157 条记录 (耗时 0.031 秒)

    Spacer T-gate structure for CoSi2 extendibility
    81.
    发明授权
    Spacer T-gate structure for CoSi2 extendibility 有权
    CoSi2可扩展性的间隔T门结构

    公开(公告)号：US07510922B2

    公开(公告)日：2009-03-31

    申请号：US11339953

    申请日：2006-01-26

    申请人： Mark D. Hall ,  Dharmesh Jawarani ,  Mehul D. Shroff ,  Edward O. Travis

    发明人： Mark D. Hall ,  Dharmesh Jawarani ,  Mehul D. Shroff ,  Edward O. Travis

    IPC分类号： H01L21/338 ,  H01L21/4763

    CPC分类号： H01L29/6656 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

    摘要： A semiconductor process and apparatus provide a T-shaped structure (84) formed from a polysilicon structure (10) and polysilicon spacers (80, 82) and having a narrower bottom dimension (e.g., at or below 40 nm) and a larger top critical dimension (e.g., at or above 40 nm) so that a silicide may be formed from a first material (such as CoSi2) in at least the upper region (100) of the T-shaped structure (84) without incurring the increased resistance caused by agglomeration and voiding that can occur with certain silicides at the smaller critical dimensions.

    摘要翻译： 半导体工艺和设备提供由多晶硅结构（10）和多晶硅间隔物（80,82）形成并且具有较窄的底部尺寸（例如，等于或低于40nm）的T形结构（84）和较大的顶部关键 尺寸（例如，在40nm以上），使得硅化物可以在至少T形结构（84）的上部区域（100）中由第一材料（例如CoSi 2）形成，而不会引起增加的电阻 通过在较小的临界尺寸下，某些硅化物可能发生的聚集和排空。

    Process of forming an electronic device including a layer formed using an inductively coupled plasma
    83.
    发明授权
    Process of forming an electronic device including a layer formed using an inductively coupled plasma 有权
    形成电子器件的工艺包括使用电感耦合等离子体形成的层

    公开(公告)号：US07491622B2

    公开(公告)日：2009-02-17

    申请号：US11409790

    申请日：2006-04-24

    申请人： Michael D. Turner ,  Mohamad M. Jahanbani ,  Toni D. Van Gompel ,  Mark D. Hall

    发明人： Michael D. Turner ,  Mohamad M. Jahanbani ,  Toni D. Van Gompel ,  Mark D. Hall

    IPC分类号： H01L21/76 ,  H01L23/58

    CPC分类号： H01L21/02274 ,  H01L21/02211 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/3185 ,  H01L21/76283 ,  H01L21/823481 ,  H01L21/84

    摘要： A process of forming an electronic device can include patterning a semiconductor layer to define an opening extending to an insulating layer, wherein the insulating layer lies between a substrate and the semiconductor layer. After patterning a semiconductor layer, the semiconductor layer can have a sidewall and a surface, the surface can be spaced apart from the insulating layer, and the sidewall can extend from the surface towards the insulating layer. The process can also include chemical vapor depositing a first layer adjacent to the sidewall, wherein the first layer lies within the opening and adjacent to the sidewall, and is spaced apart from the surface. Chemical vapor depositing the first layer can be performed using an inductively coupled plasma.

    摘要翻译： 形成电子器件的过程可以包括图案化半导体层以限定延伸到绝缘层的开口，其中绝缘层位于衬底和半导体层之间。 在图案化半导体层之后，半导体层可以具有侧壁和表面，表面可以与绝缘层间隔开，并且侧壁可以从表面延伸到绝缘层。 该方法还可以包括化学气相沉积邻近侧壁的第一层，其中第一层位于开口内且与侧壁相邻并且与表面间隔开。 可以使用电感耦合等离子体进行沉积第一层的化学气相沉积。

    Plasma treatment for surface of semiconductor device
    84.
    发明授权
    Plasma treatment for surface of semiconductor device 失效
    半导体器件表面等离子体处理

    公开(公告)号：US07176130B2

    公开(公告)日：2007-02-13

    申请号：US10987790

    申请日：2004-11-12

    申请人： Jin Miao Shen ,  Brian J. Fisher ,  Mark D. Hall ,  Kurt H. Junker ,  Vikas R. Sheth ,  Mehul D. Shroff

    发明人： Jin Miao Shen ,  Brian J. Fisher ,  Mark D. Hall ,  Kurt H. Junker ,  Vikas R. Sheth ,  Mehul D. Shroff

    IPC分类号： H01L21/441

    CPC分类号： H01L21/32139 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/0276 ,  H01L21/3105 ,  H01L21/31612

    摘要： A method for forming a semiconductor device (10) includes forming an organic anti-reflective coating (OARC) layer (18) over the semiconductor device (10). A tetra-ethyl-ortho-silicate (TEOS) layer (20) is formed over the OARC layer (18). The TEOS layer (20) is exposed to oxygen-based plasma at a temperature of at most about 300 degrees Celsius. In an alternative embodiment, the TEOS layer (20) is first exposed to a nitrogen-based plasma before being exposed to the oxygen-based plasma. A photoresist layer (22) is formed over the TEOS layer (20) and patterned. By applying oxygen based plasma and nitrogen based plasma to the TEOS layer (20) before applying photoresist, pattern defects are reduced.

    摘要翻译： 一种用于形成半导体器件（10）的方法包括在半导体器件（10）上形成有机抗反射涂层（OARC）层（18）。 在OARC层（18）上形成四乙基原硅酸盐（TEOS）层（20）。 TEOS层（20）在至多约300摄氏度的温度下暴露于基于氧的等离子体。 在替代实施例中，首先将TEOS层（20）暴露于基于氧的等离子体之前的氮基等离子体。 光致抗蚀剂层（22）形成在TEOS层（20）上并被图案化。 在施加光致抗蚀剂之前，通过将氧基等离子体和氮基等离子体施加到TEOS层（20）上，减少了图案缺陷。

    Method for elimination of excessive field oxide recess for thin Si SOI
    85.
    发明授权
    Method for elimination of excessive field oxide recess for thin Si SOI 有权
    消除薄Si SOI的过量场氧化物凹陷的方法

    公开(公告)号：US07037857B2

    公开(公告)日：2006-05-02

    申请号：US10737115

    申请日：2003-12-16

    申请人： Toni D. Van Gompel ,  Mark D. Hall ,  Mohamad Jahanbani ,  Michael D. Turner

    发明人： Toni D. Van Gompel ,  Mark D. Hall ,  Mohamad Jahanbani ,  Michael D. Turner

    IPC分类号： H01L21/3205 ,  H01L21/31

    CPC分类号： H01L21/76283

    摘要： A method for forming trench isolation in an SOI substrate begins with a pad oxide followed by an antireflective coating (ARC) over the upper semiconductor layer of the SOI substrate. The pad oxide is kept to a thickness not greater than about 100 Angstroms. An opening is formed for the trench isolation that extends into the oxide below the upper semiconductor layer to expose a surface thereof. The pad oxide is recessed along its sidewall with an isotropic etch. This is followed by a thin, not greater than 50 Angstroms, oxide grown along the sidewall of the opening. This grown oxide avoids forming a recess between the ARC and the pad oxide and also avoids forming a void between the surface of the lower oxide layer and the grown oxide. This results in avoiding polysilicon stringers when the subsequent polysilicon gate layer is formed.

    摘要翻译： 在SOI衬底中形成沟槽隔离的方法开始于衬底氧化物，然后在SOI衬底的上半导体层上方具有抗反射涂层（ARC）。 衬垫氧化物保持不大于约100埃的厚度。 形成用于沟槽隔离的开口，其延伸到上半导体层下方的氧化物中以暴露其表面。 衬垫氧化物沿其侧壁凹陷，具有各向同性蚀刻。 其后是沿着开口的侧壁生长的薄的，不大于50埃的氧化物。 这种生长的氧化物避免在ARC和衬垫氧化物之间形成凹陷，并且还避免在低氧化物层的表面和生长的氧化物之间形成空隙。 这导致当形成随后的多晶硅栅极层时避免多晶硅桁条。