公开(公告)号：US20080166856A1

公开(公告)日：2008-07-10

申请号：US12051620

申请日：2008-03-19

申请人： Kunal R. Parekh ,  Suraj Mathew ,  Jigish D. Trivedi ,  John K. Zahurak ,  Sanh D. Tang

发明人： Kunal R. Parekh ,  Suraj Mathew ,  Jigish D. Trivedi ,  John K. Zahurak ,  Sanh D. Tang

IPC分类号： H01L21/76

CPC分类号： H01L27/10876 ,  H01L27/10823

摘要： The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the recessed access device trenches, and source/drain regions are formed proximate the electrically conductive material. The electrically conductive material and source/drain regions together are incorporated into a pair of adjacent recessed access devices. After the recessed access device trenches are formed within the substrate, an isolation region trench is formed between the adjacent recessed access devices and filled with electrically insulative material to form a trenched isolation region.

摘要翻译： 本发明包括形成凹入进入装置的方法。 提供基板以在其中具有凹入的接入装置沟槽。 一对凹进的接入设备沟槽彼此相邻。 导电材料形成在凹进的存取装置沟槽内，源极/漏极区域靠近导电材料形成。 导电材料和源极/漏极区域一起被并入一对相邻的凹进入器件中。 在凹陷的访问设备沟槽形成在衬底内之后，在相邻的凹进的访问设备之间形成隔离区沟槽，并且填充有电绝缘材料以形成沟槽隔离区域。

公开(公告)号：US07332388B2

公开(公告)日：2008-02-19

申请号：US11076497

申请日：2005-03-08

申请人： Jigish D. Trivedi ,  Suraj Mathew

发明人： Jigish D. Trivedi ,  Suraj Mathew

IPC分类号： H01L21/8238

CPC分类号： H01L21/26506 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4916 ,  H01L29/66621 ,  H01L29/7834

摘要： A method for forming transistor gates having two different work functions comprises forming a first polysilicon layer which may be doped with n-type dopants. The first polysilicon layer comprises an inhibitor material at select locations which retards silicide formation. A second polysilicon layer is formed over the first polysilicon layer. The first and second polysilicon layers are masked and etched to define transistor structures, some of which comprise the inhibitor and some which are free from the inhibitor. Dielectric spacers are formed, then a metal such as cobalt is deposited over the transistor structures. A thermal process may be used to react the metal with the transistor structures to form fully silicided gates from the inhibitor-free structures and partially silicided gates from the structures comprising the inhibitor. Fully silicided gates have the work function of a metal gate while partially silicided gates may have the work function of doped polysilicon.

摘要翻译： 用于形成具有两个不同功函数的晶体管栅的方法包括形成可掺杂有n型掺杂剂的第一多晶硅层。 第一多晶硅层在选择的位置包含抑制剂材料，其阻止硅化物形成。 在第一多晶硅层上形成第二多晶硅层。 第一和第二多晶硅层被掩模和蚀刻以限定晶体管结构，其中一些包含抑制剂，一些包含不含抑制剂的晶体管结构。 形成介质间隔物，然后在晶体管结构上沉积诸如钴的金属。 可以使用热处理来使金属与晶体管结构反应，从包含抑制剂的结构的无抑制剂结构和部分硅化栅形成完全硅化的栅极。 完全硅化的栅极具有金属栅极的功函数，而部分硅化栅可具有掺杂多晶硅的功函数。

公开(公告)号：US07314822B2

公开(公告)日：2008-01-01

申请号：US11050057

申请日：2005-02-03

申请人： Jigish D. Trivedi

发明人： Jigish D. Trivedi

IPC分类号： H01L21/4763

CPC分类号： H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for forming stacked local interconnects that do not extend into higher levels within a multilevel IC device, thereby economizing space available within the IC device and increasing design flexibility. In a first embodiment, the method of the present invention provides a stacked local interconnect which electrically connects a first group of interconnected electrical features with one or more additional isolated groups of interconnected electrical features or one or more isolated individual electrical features. In a second embodiment, the method of the present invention provides a stacked local interconnect which electrically connects an individual electrical feature to one or more additional isolated electrical features.

摘要翻译： 提供了一种用于形成层叠的局部互连的方法，其不会在多电平IC器件内延伸到更高级，从而节省了IC器件内可用的空间并提高了设计灵活性。 在第一实施例中，本发明的方法提供了层叠的局部互连，其将第一组互连的电气特征与一个或多个另外的隔离的互连电特征组或一个或多个隔离的独立电气特征电连接。 在第二实施例中，本发明的方法提供了将单个电气特征电连接到一个或多个另外的隔离电气特征的堆叠局部互连。

公开(公告)号：US07279772B2

公开(公告)日：2007-10-09

申请号：US10883601

申请日：2004-06-30

申请人： Jigish D. Trivedi

发明人： Jigish D. Trivedi

IPC分类号： H01L29/00

CPC分类号： H01L23/5252 ,  G11C17/16 ,  H01L23/5254 ,  H01L27/101 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L2924/0002 ,  Y10T29/49016 ,  Y10T29/49107 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/4916 ,  Y10T29/49165 ,  H01L2924/00

摘要： An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel to a second axis, the top plate formed over the dielectric layer. Multiple edges formed at the interfaces between the top and bottom plates result in regions of localized charge concentration when a programming voltage is applied across the antifuse. As a result, the formation of the antifuse dielectric over the corners of the bottom plates enhance the electric field during programming of the antifuse. Reduced programming voltages can be used in programming the antifuse and the resulting conductive path between the top and bottom plates will likely form along the multiple edges.

公开(公告)号：US07271464B2

公开(公告)日：2007-09-18

申请号：US10925715

申请日：2004-08-24

申请人： Jigish D. Trivedi ,  Robert D. Patraw ,  Kevin L. Beaman ,  John A. Smythe, III

发明人： Jigish D. Trivedi ,  Robert D. Patraw ,  Kevin L. Beaman ,  John A. Smythe, III

IPC分类号： H01L29/00

CPC分类号： H01L21/76224 ,  H01L21/76227

摘要： A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content near the trench walls to protect the walls. The silicon nitride layer further from the trench walls has a low nitrogen content and a high silicon content, to allow improved adhesion. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator. The resulting trench has a well-adhered insulator which helps the insulating properties of the trench.

摘要翻译： 提供了将电介质材料沉积到亚微米空间和结构中的方法。 在晶片的表面蚀刻沟槽之后，将氮化硅屏障沉积到沟槽中。 氮化硅层在沟壁附近具有高氮含量以保护壁。 进一步从沟槽壁的氮化硅层具有低的氮含量和高的硅含量，以提高粘附性。 然后用旋涂前体填充沟槽。 然后施加致密化或反应过程以将旋涂材料转化成绝缘体。 所得的沟槽具有良好粘附的绝缘体，其有助于沟槽的绝缘性能。

公开(公告)号：US07210224B2

公开(公告)日：2007-05-01

申请号：US10824238

申请日：2004-04-13

申请人： Jigish D. Trivedi

发明人： Jigish D. Trivedi

IPC分类号： H05K3/02 ,  H05K3/10

CPC分类号： H01L23/5252 ,  G11C17/16 ,  H01L23/5254 ,  H01L27/101 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L2924/0002 ,  Y10T29/49016 ,  Y10T29/49107 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/4916 ,  Y10T29/49165 ,  H01L2924/00

摘要： An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel to a second axis, the top plate formed over the dielectric layer. Multiple edges formed at the interfaces between the top and bottom plates result in regions of localized charge concentration when a programming voltage is applied across the antifuse. As a result, the formation of the antifuse dielectric over the comers of the bottom plates enhance the electric field during programming of the antifuse. Reduced programming voltages can be used in programming the antifuse and the resulting conductive path between the top and bottom plates will likely form along the multiple edges.

摘要翻译： 一种反熔丝，包括具有基本上平行于第一轴线布置的多个纵向部件的底板，形成在底板上的电介质层以及具有基本平行于第二轴线布置的多个纵向部件的顶板，顶板 形成在电介质层上。 形成在顶板和底板之间的界面处的多个边缘在横跨反熔丝施加编程电压时导致局部电荷浓度的区域。 结果是，在反熔丝的编程期间，反熔丝电介质的形成在底板的角上增强了电场。 减少的编程电压可用于对反熔丝进行编程，并且可能沿着多个边缘形成顶板和底板之间的导电路径。

公开(公告)号：US07112513B2

公开(公告)日：2006-09-26

申请号：US10782997

申请日：2004-02-19

申请人： John A. Smythe, III ,  Jigish D. Trivedi

发明人： John A. Smythe, III ,  Jigish D. Trivedi

IPC分类号： H01L21/76

CPC分类号： H01L21/76224

摘要： A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an oxygen barrier is deposited into the trench. An expandable, oxidizable liner, preferably amorphous silicon, is then deposited. The trench is then filled with a spin-on dielectric (SOD) material. A densification process is then applied, whereby the SOD material contracts and the oxidizable liner expands. Preferably, the temperature is ramped up while oxidizing during at least part of the densification process. The resulting trench has a negligible vertical wet etch rate gradient and a negligible recess at the top of the trench.

摘要翻译： 提供了将电介质材料沉积到亚微米空间和结构中的方法。 在晶片的表面中蚀刻沟槽之后，将氧势垒沉积到沟槽中。 然后沉积可膨胀的可氧化衬垫，优选非晶硅。 然后用旋涂电介质（SOD）材料填充沟槽。 然后施加致密化过程，由此SOD材料收缩并且可氧化衬里膨胀。 优选地，在致密化过程的至少部分期间，温度升高而氧化。 所形成的沟槽具有可忽略的垂直湿蚀刻速率梯度和在沟槽顶部的可忽略的凹陷。

公开(公告)号：US07057218B2

公开(公告)日：2006-06-06

申请号：US10882969

申请日：2004-06-30

申请人： Jigish D. Trivedi

发明人： Jigish D. Trivedi

IPC分类号： H01L27/10

CPC分类号： H01L23/5252 ,  G11C17/16 ,  H01L23/5254 ,  H01L27/101 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L2924/0002 ,  Y10T29/49016 ,  Y10T29/49107 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/4916 ,  Y10T29/49165 ,  H01L2924/00

摘要： An antifuse including a bottom plate having a plurality of longitudinal members arranged substantially parallel to a first axis, a dielectric layer formed on the bottom plate, and a top plate having a plurality of longitudinal members arranged substantially parallel to a second axis, the top plate formed over the dielectric layer. Multiple edges formed at the interfaces between the top and bottom plates result in regions of localized charge concentration when a programming voltage is applied across the antifuse. As a result, the formation of the antifuse dielectric over the corners of the bottom plates enhance the electric field during programming of the antifuse. Reduced programming voltages can be used in programming the antifuse and the resulting conductive path between the top and bottom plates will likely form along the multiple edges.

摘要翻译： 一种反熔丝，包括具有基本上平行于第一轴线布置的多个纵向部件的底板，形成在底板上的电介质层以及具有基本平行于第二轴线布置的多个纵向部件的顶板，顶板 形成在电介质层上。 形成在顶板和底板之间的界面处的多个边缘在横跨反熔丝施加编程电压时导致局部电荷浓度的区域。 结果，在底板的角部上形成反熔丝电介质在反熔丝的编程期间增强了电场。 减少编程电压可用于对反熔丝进行编程，并且导致顶板和底板之间的导电路径很可能沿着多个边缘形成。

公开(公告)号：US06953749B2

公开(公告)日：2005-10-11

申请号：US09798404

申请日：2001-03-02

申请人： Yongjun Hu ,  Jigish D. Trivedi

发明人： Yongjun Hu ,  Jigish D. Trivedi

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76889 ,  H01L21/76895

摘要： Methods of forming refractory metal suicide components are described. In accordance with one implementation, a refractory metal layer is formed over a substrate. A silicon-containing structure is formed over the refractory metal layer and a silicon diffusion restricting layer is formed over at least some of the silicon-containing structure. The substrate is subsequently annealed at a temperature which is sufficient to cause a reaction between at least some of the refractory metal layer and at least some of the silicon-containing structure to at least partially form a refractory metal silicide component. In accordance with one aspect of the invention, a silicon diffusion restricting layer is formed over or within the refractory metal layer in a step which is common with the forming of the silicon diffusion restricting layer over the silicon-containing structure. In a preferred implementation, the silicon diffusion restricting layers are formed by exposing the substrate to nitridizing conditions which are sufficient to form a nitride-containing layer over the silicon-containing structure, and a refractory metal nitride compound within the refractory metal layer. A preferred refractory metal is titanium.

摘要翻译： 描述形成难熔金属硅化物组分的方法。 根据一个实施方案，在衬底上形成难熔金属层。 在难熔金属层之上形成含硅结构，并且在至少一些含硅结构上形成硅扩散限制层。 随后在足以使至少一些难熔金属层与至少一些含硅结构之间的反应至少部分地形成难熔金属硅化物组分的温度下进行退火。 根据本发明的一个方面，在与含硅结构上形成硅扩散限制层相同的步骤中，在难熔金属层之上或之内形成硅扩散限制层。 在优选的实施方案中，硅扩散限制层是通过将衬底暴露于足以在含硅结构上形成含氮化物层的氮化条件和难熔金属层内的难熔金属氮化物化合物而形成的。 优选的难熔金属是钛。

公开(公告)号：US06858525B2

公开(公告)日：2005-02-22

申请号：US10407957

申请日：2003-04-04

申请人： Jigish D. Trivedi

发明人： Jigish D. Trivedi

IPC分类号： H01L21/768 ,  H01L23/535 ,  H01L21/476

CPC分类号： H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is provided for forming stacked local interconnects that do not extend into higher levels within a multilevel IC device, thereby economizing space available within the IC device and increasing design flexibility. In a first embodiment, the method of the present invention provides a stacked local interconnect which electrically connects a first group of interconnected electrical features with one or more additional isolated groups of interconnected electrical features or one or more isolated individual electrical features. In a second embodiment, the method of the present invention provides a stacked local interconnect which electrically connects an individual electrical feature to one or more additional isolated electrical features.