公开(公告)号：US20170329577A1

公开(公告)日：2017-11-16

申请号：US15152266

申请日：2016-05-11

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G06F7/535 ,  G06F5/01 ,  G11C7/00

CPC classification number: G06F7/535 ,  G06F5/01 ,  G06F2205/00 ,  G06F2207/535 ,  G11C7/00 ,  G11C7/065 ,  G11C7/1006 ,  G11C11/4076 ,  G11C11/4091

Abstract: Examples of the present disclosure provide apparatuses and methods for performing signed division operations. An apparatus can include a first group of memory cells coupled to a sense line and to a number of first access lines. The apparatus can include a second group of memory cells coupled to the sense line and to a number of second access lines. The apparatus can include a controller configured to operate sensing circuitry to divide a signed dividend element stored in the first group of memory cells by a signed divisor element stored in the second group of memory cells by performing a number of operations.

公开(公告)号：US20170287530A1

公开(公告)日：2017-10-05

申请号：US15625543

申请日：2017-06-16

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari ,  Kyle B. Wheeler

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

CPC classification number: G11C7/065 ,  G11C7/1006 ,  G11C11/4091 ,  G11C19/28

Abstract: Examples of the present disclosure provide apparatuses and methods for vertical bit vector shift in a memory. An example method comprises storing a vertical bit vector of data in a memory array, wherein the vertical bit vector is stored in memory cells coupled to a sense line and a plurality of access lines and the vertical bit vector is separated by at least one sense line from a neighboring vertical bit vector; and performing, using sensing circuitry, a vertical bit vector shift of a number of elements of the vertical bit vector.

公开(公告)号：US09779789B2

公开(公告)日：2017-10-03

申请号：US15410199

申请日：2017-01-19

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G11C7/10 ,  G11C7/22 ,  G11C7/06 ,  G11C8/10 ,  G11C7/12

CPC classification number: G11C7/22 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/106 ,  G11C7/12 ,  G11C8/10

Abstract: The present disclosure includes apparatuses and methods related to performing comparison operations in memory. An example apparatus can include a first group of memory cells coupled to a first access line and configured to store a plurality of first elements, and a second group of memory cells coupled to a second access line and configured to store a plurality of second elements. The apparatus can include a controller configured to cause the plurality of first elements to be compared with the plurality of second elements by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line, and the plurality of first elements and the plurality of second elements can be compared in parallel.

公开(公告)号：US20170269903A1

公开(公告)日：2017-09-21

申请号：US15073191

申请日：2016-03-17

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G06F7/535

CPC classification number: G06F7/535

Abstract: Examples of the present disclosure provide apparatuses and methods for performing signed division operations. An apparatus can include a first group of memory cells coupled to a first access line and a number of sense lines. The apparatus can include a second group of memory cells coupled to a second access line and the number of sense lines. The apparatus can include a controller configured to cause sensing circuitry to divide a signed dividend element stored in the first group of memory cells by a signed divisor element stored in the second group of memory cells by performing a number of operations. At least one of the number of operations can be performed without transferring data via an input/output (I/O) line.

公开(公告)号：US20170236565A1

公开(公告)日：2017-08-17

申请号：US15442086

申请日：2017-02-24

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari ,  Kyle B. Wheeler

IPC: G11C7/10 ,  G11C7/12

CPC classification number: G11C7/1012 ,  G11C7/00 ,  G11C7/065 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1036 ,  G11C7/12 ,  G11C8/04 ,  G11C11/4091 ,  G11C11/4094

Abstract: Examples of the present disclosure provide apparatuses and methods related to performing a loop structure for operations performed in memory. An example apparatus might also include a controller configured to cause sensing circuitry to iterate through a plurality of first elements and a plurality of second elements via a loop structure to perform an operation using the plurality of first elements and the plurality of second elements, wherein a conditional statement associated with the loop structure is used to determine whether at least one of a plurality of bits stored as an iterator mask has a particular bit-value. An example apparatus might also include sensing circuitry controllable to perform a shift operation using the iterator mask at each iteration of the loop structure and perform an AND operation using the iterator mask at each iteration of the loop structure.

公开(公告)号：US20170236564A1

公开(公告)日：2017-08-17

申请号：US15043236

申请日：2016-02-12

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Sanjay Tiwari ,  Richard C. Murphy

IPC: G11C7/10 ,  G11C5/06

CPC classification number: G11C7/1012 ,  G11C5/06 ,  G11C5/066 ,  G11C7/1006 ,  G11C11/4091

Abstract: Examples of the present disclosure provide apparatuses and methods for storing a first element in memory cells coupled to a first sense line and a plurality of access line. The examples can include storing a second element in memory cells coupled to a second sense line and the plurality of access lines. The memory cells coupled to the first sense line can be separated from the memory cells coupled to the second sense line by at least memory cells coupled to a third sense line and the plurality of access lines. The examples can include storing the second element in the memory cells coupled to the third sense line.

公开(公告)号：US20170186468A1

公开(公告)日：2017-06-29

申请号：US15457339

申请日：2017-03-13

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G11C7/10 ,  G11C7/06

CPC classification number: G11C7/1036 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C11/4091 ,  G11C11/4096

Abstract: Examples of the present disclosure provide apparatuses and methods for performing shift operations in a memory. An example method comprises performing a shift operation a first element stored in a first group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a second group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include shifting the first element by a number of bit positions defined by the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations performed without transferring data via an input/output (I/O) line.

公开(公告)号：US09659605B1

公开(公告)日：2017-05-23

申请号：US15133861

申请日：2016-04-20

Applicant: Micron Technology, Inc.

Inventor： Jason T. Zawodny ,  Sanjay Tiwari

IPC: G11C7/10 ,  G11C7/06 ,  G11C7/14 ,  G11C7/00 ,  G11C16/26 ,  G11C16/10 ,  G11C16/24

CPC classification number: G11C7/1012 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0685 ,  G06F13/1663 ,  G11C7/065 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1036 ,  G11C7/22 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C2207/005 ,  G11C2211/5641

Abstract: The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a first group of memory cells coupled to an access line and a plurality of sense lines and a second group of memory cells coupled to a plurality of access lines and a sense line. The example apparatus comprises a controller configured to cause a corner turn operation using sensing circuitry on an element stored in the first group of memory cells resulting in the element being stored in the second group of memory cells.

公开(公告)号：US20160196856A1

公开(公告)日：2016-07-07

申请号：US14978583

申请日：2015-12-22

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari ,  Kyle B. Wheeler

IPC: G11C7/10 ,  G06F9/30 ,  G11C7/06

CPC classification number: G11C7/1012 ,  G11C7/065 ,  G11C7/1006 ,  G11C11/4091 ,  G11C11/4096 ,  G11C19/28 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2207/007

Abstract: Examples of the present disclosure provide apparatuses and methods for determining a length of a longest element in a memory. An example method comprises determining, using a controller to control sensing circuitry, a length of a longest element of a plurality of variable length elements of a vector stored in a memory array.

Abstract translation: 本公开的示例提供了用于确定存储器中最长元素的长度的装置和方法。 示例性方法包括：使用控制器来控制感测电路，存储在存储器阵列中的矢量的多个可变长度元素中的最长元素的长度。

公开(公告)号：US20160064047A1

公开(公告)日：2016-03-03

申请号：US14836726

申请日：2015-08-26

Applicant: Micron Technology, Inc.

Inventor： Sanjay Tiwari

IPC: G11C7/06

CPC classification number: G11C7/22 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/106 ,  G11C7/12 ,  G11C8/10

Abstract: The present disclosure includes apparatuses and methods related to performing comparison operations in memory. An example apparatus can include a first group of memory cells coupled to a first access line and configured to store a plurality of first elements, and a second group of memory cells coupled to a second access line and configured to store a plurality of second elements. The apparatus can include a controller configured to cause the plurality of first elements to be compared with the plurality of second elements by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line, and the plurality of first elements and the plurality of second elements can be compared in parallel.

Abstract translation: 本公开包括与在存储器中执行比较操作有关的装置和方法。 示例性设备可以包括耦合到第一接入线路并被配置为存储多个第一元件的第一组存储器单元，以及耦合到第二接入线路并被配置为存储多个第二元件的第二组存储器单元。 该装置可以包括：控制器，被配置为通过控制感测电路来执行多个操作而不经由输入/输出（I / O）线传输数据，使多个第一元件与多个第二元件进行比较， 可以并行地比较多个第一元件和多个第二元件。