公开(公告)号：US11023164B2

公开(公告)日：2021-06-01

申请号：US16012736

申请日：2018-06-19

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/04

Abstract: Apparatus and methods are disclosed, including identifying and tagging data in a group of volatile memory cells of a host device to be written to and maintained contiguously on non-volatile memory of a storage system, and writing the tagged data to the group of non-volatile memory cells. A host device includes a host processor and the group of volatile memory cells, and a storage system includes the group of non-volatile memory cells.

公开(公告)号：US20210109756A1

公开(公告)日：2021-04-15

申请号：US17129203

申请日：2020-12-21

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean

IPC: G06F9/30 ,  G06F13/16 ,  G06F13/18

Abstract: Devices and techniques for implementing quality-of-service (QoS) parameters in a managed memory device having a number of memory dies are disclosed herein.

公开(公告)号：US20210048961A1

公开(公告)日：2021-02-18

申请号：US17084289

申请日：2020-10-29

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/10

Abstract: Apparatus and methods are disclosed, including providing available data operations for the storage system processor to a host processor, identifying data operations to be performed by the storage system processor, and assigning identified data operations to the storage system processor to reduce bus traffic between the host processor and the storage system processor, to improve host processor performance, and to reduce energy use by the host processor.

公开(公告)号：US10916316B2

公开(公告)日：2021-02-09

申请号：US17016182

申请日：2020-09-09

Applicant: Micron Technology, Inc.

Inventor： Greg A. Blodgett ,  Sebastien Andre Jean

IPC: G06F12/14 ,  G11C16/34 ,  G11C16/04 ,  G06F1/3206 ,  G11C7/04 ,  G06F3/06 ,  G06F9/30 ,  G06F9/32 ,  G06F9/54 ,  G06F12/02 ,  G06F21/79 ,  H04L9/08 ,  G11C16/10

Abstract: Apparatus and methods are disclosed, including a memory device or a memory controller configured to determine that a condition has occurred that indicates a performance throttling operation, implement a performance throttling responsive to the determined condition, responsive to implementing the performance throttling, set a performance throttling status indicator in an exception event status attribute, receive a command from a host device across a memory device interface, perform the command, prepare a response to the command, the response including a flag indicating that the performance throttling status indicator is set in the exception event status attribute, and send the response to the host device. Methods of operation are disclosed, as well as machine-readable medium and other embodiments.

公开(公告)号：US10790032B2

公开(公告)日：2020-09-29

申请号：US16542963

申请日：2019-08-16

Applicant: Micron Technology, Inc.

Inventor： Greg A. Blodgett ,  Sebastien Andre Jean

IPC: G06F12/14 ,  G11C16/34 ,  G11C16/04 ,  G06F1/3206 ,  G11C7/04 ,  G06F3/06 ,  G11C16/10

Abstract: Apparatus and methods are disclosed, including a memory device or a memory controller configured to determine that a condition has occurred that indicates a performance throttling operation, implement a performance throttling responsive to the determined condition, responsive to implementing the performance throttling, set a performance throttling status indicator in an exception event status attribute, receive a command from a host device across a memory device interface, perform the command, prepare a response to the command, the response including a flag indicating that the performance throttling status indicator is set in the exception event status attribute, and send the response to the host device. Methods of operation are disclosed, as well as machine-readable medium and other embodiments.

公开(公告)号：US20200218672A1

公开(公告)日：2020-07-09

申请号：US16628453

申请日：2018-06-29

Applicant: Micron Technology, Inc.

Inventor： Greg A. Blodgett ,  Sebastien Andre Jean

IPC: G06F12/14 ,  G06F12/02 ,  G06F9/30 ,  G06F9/32 ,  G06F9/54 ,  G06F21/79 ,  H04L9/08

Abstract: Apparatus and methods are disclosed, including a memory device or a memory controller configured to supply supported voltages to a host, provide temperature throttling information to the host, or provide an indication that a host attempting to read a result was not the host that caused the placement of the result in a result register. Methods of operation are disclosed, as well as machine-readable medium and other embodiments.

公开(公告)号：US10699780B2

公开(公告)日：2020-06-30

申请号：US16209152

申请日：2018-12-04

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean ,  Ting Luo

IPC: G11C11/56 ,  G11C16/34 ,  G11C16/10

Abstract: Devices and techniques to reduce corruption of received data during assembly are disclosed herein. A memory device can perform operations to store received data, including preloaded data, in a first mode until the received data exceeds a threshold amount, and to transition from the first mode to a second mode after the received data exceeds the threshold amount.

公开(公告)号：US20200159426A1

公开(公告)日：2020-05-21

申请号：US16773334

申请日：2020-01-27

Applicant: Micron Technology, Inc.

Inventor： Kulachet Tanpairoj ,  Sebastien Andre Jean ,  Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Jianmin Huang

IPC: G06F3/06 ,  G06F12/0811 ,  G06F12/02

Abstract: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The SLC memory cells serve as a high-speed cache providing SLC level performance with the storage capacity of a memory device with MLC memory cells. The proportion of cells configured as MLC vs the proportion that are configured as SLC storage may be configurable, and in some examples, the proportion may change during usage based upon configurable rules based upon memory device metrics. In some examples, when the device activity is below an activity threshold, the memory device may skip the SLC cache and place the data directly into the MLC storage to reduce power consumption.

公开(公告)号：US20200004689A1

公开(公告)日：2020-01-02

申请号：US16568962

申请日：2019-09-12

Applicant: Micron Technology, Inc.

Inventor： Sebastien Andre Jean

IPC: G06F12/1009

Abstract: Devices and techniques for memory constrained translation table management are disclosed herein. A level of a translation table is logically segmented into multiple segments. Here, a bottom level of the translation table includes a logical to physical address pairing for a portion of a storage device and other levels of the translation table include references within the translation table. The multiple segments are written to the storage device. A first segment of the multiple segments is loaded to byte-addressable memory. A request for an address translation is received and determined to be for an address referred to by a second segment of the multiple segments. The first segment is then replaced with the second segment in the byte-addressable memory and the request is fulfilled using the second segment to locate a lower level of the translation table that includes the address translation.

公开(公告)号：US10522229B2

公开(公告)日：2019-12-31

申请号：US15691584

申请日：2017-08-30

Applicant: Micron Technology, Inc.

Inventor： Ting Luo ,  Kulachet Tanpairoj ,  Harish Singidi ,  Jianmin Huang ,  Preston Thomson ,  Sebastien Andre Jean

IPC: G11C11/34 ,  G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  G11C11/56 ,  G11C16/34 ,  H01L27/11582 ,  H01L27/11556

Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.