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    MICROELECTRONIC DEVICES INCLUDING SLOT STRUCTURES AND ADDITIONAL SLOT STRUCTURES, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS
    81.
    发明申请
    MICROELECTRONIC DEVICES INCLUDING SLOT STRUCTURES AND ADDITIONAL SLOT STRUCTURES, AND RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS 有权

    公开(公告)号：US20250098158A1

    公开(公告)日：2025-03-20

    申请号：US18966674

    申请日：2024-12-03

    Applicant: Micron Technology, Inc.

    Inventor： Shuangqiang Luo ,  Brett D. Lowe

    IPC: H10B41/27 ,  G11C5/02 ,  G11C5/06 ,  H01L23/528 ,  H10B43/27

    Abstract: A microelectronic device comprises a stack structure, slot structures vertically extending completely through the stack structure, and support pillar structures vertically extending through the stack structure. The stack structure comprises tiers vertically stacked relative to one another, each tier including a conductive material and insulative material vertically neighboring the conductive material. The stack structure includes a staircase structure therein comprising steps defined by edges of at least some of the tiers. The support pillar structures are arranged in rows horizontally extending in a first direction. The slot structures divide the stack structure into block structures. The microelectronic device further comprises additional slot structures within a horizontal area of one of the block structures. The additional slot structures include a first additional slot structure at least partially intersecting one of the rows of the support pillar structures. The additional slot structures also include a second additional slot structure horizontally spaced apart from the first additional slot structure and each of the rows of the support pillar structures in a second direction orthogonal to the first direction.

    Integrated Assemblies and Methods of Forming Integrated Assemblies
    82.
    发明申请
    Integrated Assemblies and Methods of Forming Integrated Assemblies 有权

    公开(公告)号：US20250056802A1

    公开(公告)日：2025-02-13

    申请号：US18930589

    申请日：2024-10-29

    Applicant: Micron Technology, Inc.

    Inventor： Shuangqiang Luo ,  Dong Wang ,  Rui Zhang ,  Da Xing ,  Xiao Li ,  Pei Qiong Cheung ,  Xiao Zeng

    IPC: H10B43/27 ,  H10B41/27 ,  H10B41/40 ,  H10B43/40

    Abstract: Some embodiments include an assembly having conductive structures distributed along a level within a memory array region and another region proximate the memory array region. The conductive structures include a first stack over a metal-containing region. A semiconductor material is within the first stack. A second stack is over the conductive structures, and includes alternating conductive tiers and insulative tiers. Cell-material-pillars are within the memory array region. The cell-material-pillars include channel material. The semiconductor material directly contacts the channel material. Conductive post structures are within the other region. Some of the conductive post structures are dummy structures and have bottom surfaces which are entirely along an insulative oxide material. Others of the conductive post structures are live posts electrically coupled with CMOS circuitry. Some embodiments include methods of forming assemblies.

    Integrated assemblies and methods of forming integrated assemblies
    83.
    发明授权
    Integrated assemblies and methods of forming integrated assemblies 有权

    公开(公告)号：US12167604B2

    公开(公告)日：2024-12-10

    申请号：US18381791

    申请日：2023-10-19

    Applicant: Micron Technology, Inc.

    Inventor： Shuangqiang Luo ,  Dong Wang ,  Rui Zhang ,  Da Xing ,  Xiao Li ,  Pei Qiong Cheung ,  Xiao Zeng

    IPC: H10B43/27 ,  H10B41/27 ,  H10B41/40 ,  H10B43/40

    Abstract: Some embodiments include an assembly having conductive structures distributed along a level within a memory array region and another region proximate the memory array region. The conductive structures include a first stack over a metal-containing region. A semiconductor material is within the first stack. A second stack is over the conductive structures, and includes alternating conductive tiers and insulative tiers. Cell-material-pillars are within the memory array region. The cell-material-pillars include channel material. The semiconductor material directly contacts the channel material. Conductive post structures are within the other region. Some of the conductive post structures are dummy structures and have bottom surfaces which are entirely along an insulative oxide material. Others of the conductive post structures are live posts electrically coupled with CMOS circuitry. Some embodiments include methods of forming assemblies.

    Memory Circuitry And Methods Used In Forming Memory Circuitry
    85.
    发明公开
    Memory Circuitry And Methods Used In Forming Memory Circuitry 审中-公开

    公开(公告)号：US20240341095A1

    公开(公告)日：2024-10-10

    申请号：US18602321

    申请日：2024-03-12

    Applicant: Micron Technology, Inc.

    Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Kar Wui Thong

    IPC: H10B43/27 ,  H10B41/27

    CPC classification number: H10B43/27 ,  H10B41/27

    Abstract: Memory circuitry comprising strings of memory cells comprises vertically-alternating insulative tiers and conductive tiers that extend from a memory-array region into a stair-step region across an intermediate region that is between the memory-array region and the stair-step region. The insulative tiers and the conductive tiers comprise memory blocks upper portions of which individually comprise sub-blocks. Sub-block trenches are in the upper portions individually between immediately-laterally-adjacent of the sub-blocks. Strings of memory cells in the memory-array region comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks and in the sub-blocks. The sub-block trenches in the memory-array region, in the intermediate region, and in the stair-step region individually have a top. The top of individual of the sub-block trenches in the stair-step region has a narrowest-width that is larger than a narrowest-width of the top of the individual sub-block trenches in the intermediate region. The narrowest-width of the top of the individual sub-block trenches in the intermediate region is larger than a narrowest-width of the top of the individual sub-block trenches in the memory-array region. Other embodiments, including method, are disclosed.

    MERGED CAVITIES FOR CONDUCTOR FORMATION IN A MEMORY DIE
    86.
    发明公开
    MERGED CAVITIES FOR CONDUCTOR FORMATION IN A MEMORY DIE 审中-公开

    公开(公告)号：US20240284672A1

    公开(公告)日：2024-08-22

    申请号：US18443013

    申请日：2024-02-15

    Applicant: Micron Technology, Inc.

    Inventor： David H. Wells ,  Matthew J. King ,  Indra V. Chary ,  Yoshiaki Fukuzumi ,  Lifang Xu ,  Paolo Tessariol ,  Shuangqiang Luo

    IPC: H10B43/27 ,  H10B43/10

    CPC classification number: H10B43/27 ,  H10B43/10

    Abstract: Methods, systems, and devices for merged cavities for conductor formation in a memory die are described. An array of cavities may be formed through a stack of material layers of a memory die, and conductors may be formed at least in part by merging some of the cavities of the array. Such cavities may be sized in accordance with a relatively smallest feature that implements a subset of such cavities, and a smallest associated feature may be formed using a first subset of the array of cavities. Conductors may be formed at least in part by merging two or more cavities of a second subset of the array of cavities using a material removal operation to remove portions of the stack of material layers. Such merging may support conductors being formed with a cross-section that is greater than a cross-section of other features formed using such cavities that are not merged.

    MEMORY DEVICE INCLUDING SOURCE STRUCTURE HAVING CONDUCTIVE ISLANDS OF DIFFERENT WIDTHS
    89.
    发明公开
    MEMORY DEVICE INCLUDING SOURCE STRUCTURE HAVING CONDUCTIVE ISLANDS OF DIFFERENT WIDTHS 审中-公开

    公开(公告)号：US20230395501A1

    公开(公告)日：2023-12-07

    申请号：US18202061

    申请日：2023-05-25

    Applicant: Micron Technology, Inc.

    Inventor： Shuangqiang Luo

    IPC: H01L23/528 ,  G11C16/04 ,  H10B41/10 ,  H10B41/35 ,  H10B41/27

    CPC classification number: H01L23/5283 ,  G11C16/0483 ,  H10B41/10 ,  H10B41/35 ,  H10B41/27

    Abstract: Some embodiments include apparatuses. One of the apparatuses includes a conductive structure including a first conductive region under first memory cells, a second conductive region under second memory cells, and a third conductive region between the first and second conductive regions; conductive islands adjacent each other and formed in the third conductive region and separated from the third conductive region; dielectric isolators separating the conductive islands from each other, wherein the conductive islands include a conductive island such that a first portion of the conductive islands is located on a first side of the conductive island, and a second portion of the conductive islands is located on a second side of the conductive island; and the width of the conductive island is greater than the width of at least one conductive island in each of the first and second portions of the conductive islands.

    MEMORY DEVICE INCLUDING CONTACT STRUCTURES HAVING MULTI-LAYER DIELECTRIC LINER
    90.
    发明公开
    MEMORY DEVICE INCLUDING CONTACT STRUCTURES HAVING MULTI-LAYER DIELECTRIC LINER 审中-公开

    公开(公告)号：US20230387023A1

    公开(公告)日：2023-11-30

    申请号：US17826776

    申请日：2022-05-27

    Applicant: Micron Technology, Inc.

    Inventor： Shuangqiang Luo

    IPC: H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

    CPC classification number: H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

    Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes tiers located one over another, the tiers including respective memory cells and control gates for the memory cells; conductive contacts contacting the control gates, the conductive contacts having different lengths extending in a direction from one tier to another tier among the tiers; and a contact structure adjacent one of the conductive contacts. The contact structure includes a conductive core portion extending through the tiers and separated from the control gates, and a dielectric liner portion adjacent the conductive core portion. The dielectric liner portion includes a first dielectric material, a second dielectric material adjacent the first dielectric material, and a third dielectric material adjacent the second dielectric material.

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