公开(公告)号：US20220359398A1

公开(公告)日：2022-11-10

申请号：US17314485

申请日：2021-05-07

Applicant: Micron Technology, Inc.

Inventor： Lingyu Kong ,  Lifang Xu ,  Indra V. Chary ,  Shuangqiang Luo ,  Sok Han Wong

IPC: H01L23/535 ,  H01L23/528 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11582 ,  H01L21/768

Abstract: A microelectronic device comprises a stack structure comprising insulative structures vertically interleaved with conductive structures, first support pillar structures vertically extending through the stack structure in a first staircase region including steps defined at edges of tiers of the insulative structures and conductive structures, and second support pillar structures vertically extending through the stack structure in a second staircase region including additional steps defined at edges of additional tiers of the insulative structures and conductive structures, the second support pillar structures having a smaller cross-sectional area than the first support pillar structures. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US12040274B2

公开(公告)日：2024-07-16

申请号：US17314485

申请日：2021-05-07

Applicant: Micron Technology, Inc.

Inventor： Lingyu Kong ,  Lifang Xu ,  Indra V. Chary ,  Shuangqiang Luo ,  Sok Han Wong

IPC: H10B41/27 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H01L23/535 ,  H10B43/27

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/562 ,  H10B41/27 ,  H10B43/27

Abstract: A microelectronic device comprises a stack structure comprising insulative structures vertically interleaved with conductive structures, first support pillar structures vertically extending through the stack structure in a first staircase region including steps defined at edges of tiers of the insulative structures and conductive structures, and second support pillar structures vertically extending through the stack structure in a second staircase region including additional steps defined at edges of additional tiers of the insulative structures and conductive structures, the second support pillar structures having a smaller cross-sectional area than the first support pillar structures. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US20240188299A1

公开(公告)日：2024-06-06

申请号：US18525362

申请日：2023-11-30

Applicant: Micron Technology, Inc.

Inventor： Christopher J. Larsen ,  S M Istiaque Hossain ,  David A. Daycock ,  Kevin R. Gast ,  George Matamis ,  Lingyu Kong ,  Sok Han Wong ,  Lhaang Chee Ooi ,  Wenjie Li

IPC: H10B43/27 ,  G11C16/04 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  G11C16/0483 ,  H10B43/10 ,  H10B43/35

Abstract: Methods, systems, and devices for three-dimensional memory array formation techniques are described. A memory device may include a stack of materials over a substrate. The memory device may include an array of first pillars and an array of second pillars extending at least partially through the stack of materials. One or more first pillars may be excluded from one or more columns of pillars of the array first pillars. The memory device may include dielectric material in a slit extending at least partially through the stack of materials. Based on the exclusion of the one or more first pillars, the slit may have a greater width at a first portion through the stack of materials than a second portion through the stack of materials. The dielectric material located in the slit may also have a greater width at the first portion than at the second portion.

公开(公告)号：US20240347464A1

公开(公告)日：2024-10-17

申请号：US18752525

申请日：2024-06-24

Applicant: Micron Technology, Inc.

Inventor： Lingyu Kong ,  Lifang Xu ,  Indra V. Chary ,  Shuangqiang Luo ,  Sok Han Wong

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/00 ,  H01L23/528 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/562 ,  H10B41/27 ,  H10B43/27

Abstract: A microelectronic device comprises a stack structure comprising insulative structures vertically interleaved with conductive structures, first support pillar structures vertically extending through the stack structure in a first staircase region including steps defined at edges of tiers of the insulative structures and conductive structures, and second support pillar structures vertically extending through the stack structure in a second staircase region including additional steps defined at edges of additional tiers of the insulative structures and conductive structures, the second support pillar structures having a smaller cross-sectional area than the first support pillar structures. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US20230389311A1

公开(公告)日：2023-11-30

申请号：US17804752

申请日：2022-05-31

Applicant: Micron Technology, Inc.

Inventor： Yifen Liu ,  Xin Lan ,  Byeung Chul Kim ,  Ye Xiang Hong ,  Yun Huang ,  Sok Han Wong

IPC: H01L27/11578 ,  H01L27/11565 ,  H01L29/06

CPC classification number: H01L27/11578 ,  H01L27/11565 ,  H01L29/0649

Abstract: An electronic device includes a stack structure including vertically alternating dielectric materials and conductive materials, the conductive materials including first regions and second regions, and pillars extending vertically through the stack structure, the pillars adjacent to the second regions of the conductive materials. The pillars include cell films adjacent to the second regions, the cell films including a high-k dielectric material, a barrier oxide material, a storage node material, a tunneling material, and a channel material. Segments of each of the high-k dielectric material, the barrier oxide material, and the storage node material are adjacent to the second regions. A length of the segments of high-k dielectric material and a length of the segments of storage node material adjacent to the second regions are greater than a height of the first regions of the conductive materials. Related methods and systems are also disclosed.

公开(公告)号：US20230413550A1

公开(公告)日：2023-12-21

申请号：US17807074

申请日：2022-06-15

Applicant: Micron Technology, Inc.

Inventor： Lingyu Kong ,  Sok Han Wong

IPC: H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L21/31111

Abstract: An electronic device comprises a source stack comprising one or more conductive materials. A source contact is adjacent to the source stack and a source seal is on a portion of the source contact. Tiers of alternating conductive materials and dielectric materials are adjacent to the source contact. Pillars extend through the tiers and the source contact and into the source stack. Additional electronic devices, electronic systems, and methods of forming the electronic devices are disclosed.

公开(公告)号：US20220399363A1

公开(公告)日：2022-12-15

申请号：US17348460

申请日：2021-06-15

Applicant: Micron Technology, Inc.

Inventor： Lingyu Kong ,  Sok Han Wong

IPC: H01L27/11582 ,  H01L27/11556

Abstract: Integrated circuitry comprising a memory array comprises strings of memory cells comprising laterally-spaced memory blocks individually comprising a first vertical stack comprising alternating insulative tiers and conductive tiers. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The conductive tiers individually comprise a horizontally-elongated conductive line. A second vertical stack is aside the first vertical stack. The second vertical stack comprises an upper portion and a lower portion. The upper portion comprises vertically alternating first tiers and second insulating tiers that are of different composition relative one another. The lower portion comprises an upper polysilicon-comprising layer, a lower polysilicon-comprising layer, an intervening-material layer vertically between the upper and lower polysilicon-comprising layers. An upper intermediate layer is vertically between the upper polysilicon-comprising layer and the intervening-material layer. A lower intermediate layer is vertically between the lower polysilicon-comprising layer and the intervening-material layer. The lower intermediate layer and the upper intermediate layer comprise at least one of (a), (b), and (c), where (a): SiNx, where “x” is greater than 1.33 and no more than 2.0, or alternately where “x” is 0.5 to less than 1.33; (b): a bilayer comprising SiNy and comprising silicon dioxide positioned vertically relative one another, where “y” is 0.5 to no more than 2.0, the silicon dioxide of the bilayer being closer to the sacrificial material of the lowest first tier than is the SiNy; and (c): carbon-doped SiNz having carbon present at 0.1 to 10.0 atomic percent, “z” being 0.5 to no more than 2.0. Methods are disclosed.