公开(公告)号：US20180330767A1

公开(公告)日：2018-11-15

申请号：US15595171

申请日：2017-05-15

Applicant: Micron Technology, Inc.

Inventor： Perry V. Lea ,  Troy A. Manning

IPC: G11C7/10 ,  H03K19/173 ,  G06F13/12 ,  G06F12/02 ,  G06F3/06

CPC classification number: G11C7/1006 ,  G06F3/0683 ,  G06F12/02 ,  G06F12/0238 ,  G06F13/124 ,  G06F2003/0692 ,  H03K19/1733

Abstract: The present disclosure includes apparatuses and methods for bank to bank data transfer. An example apparatus includes a plurality of banks of memory cells, an internal bus configured to transfer data between the plurality of banks and an external bus interface, and a bank-to-bank transfer bus configured to transfer data between the plurality of banks.

公开(公告)号：US10061590B2

公开(公告)日：2018-08-28

申请号：US14980024

申请日：2015-12-28

Applicant: Micron Technology, Inc.

Inventor： Kyle B. Wheeler ,  Richard C. Murphy ,  Troy A. Manning ,  Dean A. Klein

IPC: G06F9/38 ,  G06F15/78 ,  G11C7/06 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4096

CPC classification number: G06F9/3877 ,  G06F15/7821 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1036 ,  G11C11/4087 ,  G11C11/4096

Abstract: The present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array.

公开(公告)号：US09892766B2

公开(公告)日：2018-02-13

申请号：US15270761

申请日：2016-09-20

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C7/00 ,  G11C7/06 ,  G06F12/00 ,  G11C7/10 ,  G11C15/00 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4094

CPC classification number: G11C7/065 ,  G06F12/00 ,  G11C7/1006 ,  G11C7/1051 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C15/00

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.

公开(公告)号：US09786335B2

公开(公告)日：2017-10-10

申请号：US14725956

申请日：2015-05-29

Applicant: Micron Technology, Inc.

Inventor： Glen E. Hush ,  Troy A. Manning

IPC: G11C7/00 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4093 ,  G11C7/06 ,  G11C11/16

CPC classification number: G11C7/00 ,  G11C7/065 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1012 ,  G11C11/1673 ,  G11C11/4091 ,  G11C11/4093

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier coupled to a pair of complementary sense lines, and a compute component coupled to the sense amplifier. The compute component includes a dynamic latch. The sensing circuitry is configured to perform a logical operation and initially store the result in the sense amplifier.

公开(公告)号：US09589607B2

公开(公告)日：2017-03-07

申请号：US15051112

申请日：2016-02-23

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C7/06 ,  G06F3/06 ,  G11C7/10 ,  G06F12/00 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4091 ,  G06F7/523 ,  H03K19/00

CPC classification number: G11C7/22 ,  G06F3/0611 ,  G06F3/0625 ,  G06F3/065 ,  G06F3/068 ,  G06F7/523 ,  G06F12/00 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1087 ,  G11C11/4074 ,  G11C11/4091 ,  H03K19/0013 ,  H03K19/1776

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.

Abstract translation: 本公开包括与使用感测电路执行逻辑运算相关的装置和方法。 示例性设备包括存储器单元阵列和感测电路，该电路包括耦合到该阵列的感测线的主锁存器。 感测电路可以被配置为通过感测耦合到感测线的存储器单元来执行逻辑操作的第一操作阶段，通过感测耦合到所述逻辑操作的相应数量的不同存储器单元执行逻辑操作的多个中间操作阶段 并且在不执行感测线地址访问的情况下，累积第一操作阶段的结果和耦合到主锁存器的次锁存器中的中间操作相位的数量。

公开(公告)号：US20170011782A1

公开(公告)日：2017-01-12

申请号：US15270761

申请日：2016-09-20

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C7/06 ,  G11C11/4091

CPC classification number: G11C7/065 ,  G06F12/00 ,  G11C7/1006 ,  G11C7/1051 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C15/00

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry is configured to perform a logical operation using a data value stored in a first memory cell coupled to a sense line as a first input and a data value stored in a second memory cell coupled to the sense line as a second input. The sensing circuitry is configured to perform the logical operation without transferring data via a sense line address access.

Abstract translation: 本公开包括与使用感测电路执行逻辑运算相关的装置和方法。 示例性设备包括耦合到阵列的存储器单元阵列和感测电路。 感测电路被配置为使用存储在耦合到感测线的第一存储器单元中的数据值作为第一输入和存储在耦合到感测线的第二存储器单元中的数据值作为第二输入来执行逻辑运算。 感测电路被配置为执行逻辑操作而不经由感测线地址访问传送数据。

公开(公告)号：US09483203B2

公开(公告)日：2016-11-01

申请号：US14053831

申请日：2013-10-15

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G06F12/00 ,  G06F3/06 ,  G06F11/20 ,  G06F12/02 ,  G11C16/34 ,  G11C29/00

CPC classification number: G06F3/065 ,  G06F3/0619 ,  G06F3/0679 ,  G06F11/2069 ,  G06F11/2087 ,  G06F12/0246 ,  G11C16/349 ,  G11C29/74

Abstract: The present disclosure includes methods and devices for operating a solid state drive. One method embodiment includes mirroring programming operations such that data associated with a programming operation is programmed to two or more locations in memory of the solid state drive. The method also includes ceasing to mirror programming operations upon an occurrence of a particular event.

公开(公告)号：US09466340B2

公开(公告)日：2016-10-11

申请号：US14603850

申请日：2015-01-23

Applicant: Micron Technology, Inc.

Inventor： Troy A. Manning

IPC: G11C7/12 ,  G11C7/06 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G11C7/065 ,  G11C7/06 ,  G11C7/062 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4096 ,  G11C15/043

Abstract: The present disclosure includes apparatuses and methods related to performing compare and/or report operations using sensing circuitry. An example method can include charging an input/output (IO) line of a memory array to a voltage. The method can include determining whether data stored in the memory array matches a compare value. The determination of whether data stored matches a compare value can include activating a number of access lines of the memory array. The determination can include sensing a number of memory cells coupled to the number of access lines. The determination can include sensing whether the voltage of the IO line changes in response to activation of selected decode lines corresponding to the number of memory cells.

公开(公告)号：US20150357024A1

公开(公告)日：2015-12-10

申请号：US14725956

申请日：2015-05-29

Applicant: Micron Technology, Inc.

Inventor： Glen E. Hush ,  Troy A. Manning

IPC: G11C11/4091 ,  G11C11/4093

CPC classification number: G11C7/00 ,  G11C7/065 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1012 ,  G11C11/1673 ,  G11C11/4091 ,  G11C11/4093

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier coupled to a pair of complementary sense lines, and a compute component coupled to the sense amplifier. The compute component includes a dynamic latch. The sensing circuitry is configured to perform a logical operation and initially store the result in the sense amplifier.

Abstract translation: 本公开包括与使用感测电路执行逻辑运算相关的装置和方法。 示例性设备包括耦合到阵列的存储器单元阵列和感测电路。 感测电路包括耦合到一对互补检测线的读出放大器和耦合到读出放大器的计算部件。 计算组件包括一个动态锁存器。 感测电路被配置为执行逻辑操作并且最初将结果存储在读出放大器中。

公开(公告)号：US20150357019A1

公开(公告)日：2015-12-10

申请号：US14715001

申请日：2015-05-18

Applicant: Micron Technology, Inc.

Inventor： Kyle B. Wheeler ,  Troy A. Manning ,  Richard C. Murphy

IPC: G11C11/4091

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4096

Abstract: One example of the present disclosure includes performing a comparison operation in memory using a logical representation of a first value stored in a first portion of a number of memory cells coupled to a sense line of a memory array and a logical representation of a second value stored in a second portion of the number of memory cells coupled to the sense line of the memory array. The comparison operation compares the first value to the second value, and the method can include storing a logical representation of a result of the comparison operation in a third portion of the number of memory cells coupled to the sense line of the memory array.

Abstract translation: 本公开的一个示例包括使用存储在耦合到存储器阵列的感测线的多个存储器单元的第一部分中的第一值的逻辑表示和存储的第二值的逻辑表示来在存储器中执行比较操作 在耦合到存储器阵列的感测线的存储器单元的数量的第二部分中。 比较操作将第一值与第二值进行比较，并且该方法可以包括将比较操作的结果的逻辑表示存储在耦合到存储器阵列的感测线的存储器单元的数量的第三部分中。