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94 条记录 (耗时 0.028 秒)

    Assigning Memory to On-Chip Coherence Domains
    81.
    发明申请
    Assigning Memory to On-Chip Coherence Domains 有权
    将内存分配给片上一致性域

    公开(公告)号：US20120265944A1

    公开(公告)日：2012-10-18

    申请号：US13454814

    申请日：2012-04-24

    申请人： William E. Speight ,  Lixin Zhang

    发明人： William E. Speight ,  Lixin Zhang

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0831

    摘要： A mechanism for assigning memory to on-chip cache coherence domains assigns caches within a processing unit to coherence domains. The mechanism assigns chunks of memory to the coherence domains. The mechanism monitors applications running on cores within the processing unit to identify needs of the applications. The mechanism may then reassign memory chunks to the cache coherence domains based on the needs of the applications running in the coherence domains. When a memory controller receives the cache miss, the memory controller may look up the address in a lookup table that maps memory chunks to cache coherence domains. Snoop requests are sent to caches within the coherence domain. If a cache line is found in a cache within the coherence domain, the cache line is returned to the originating cache by the cache containing the cache line either directly or through the memory controller.

    摘要翻译： 将存储器分配给片上高速缓存一致性域的机制将处理单元内的高速缓存分配给相干域。 该机制将大块内存分配给一致性域。 该机制监视在处理单元内的核心上运行的应用程序，以识别应用程序的需求。 然后，该机制可以基于在相干域中运行的应用的需要将存储器块重新分配给高速缓存一致性域。 当存储器控制器接收高速缓存未命中时，存储器控制器可以查找映射内存块到高速缓存一致性域的查找表中的地址。 侦听请求被发送到连贯域内的缓存。 如果在相干域内的高速缓存中找到高速缓存行，则通过直接或通过存储器控制器的高速缓存行的高速缓存将高速缓存行返回到始发高速缓存。

    Techniques for prediction-based indirect data prefetching
    82.
    发明授权
    Techniques for prediction-based indirect data prefetching 有权
    基于预测的间接数据预取技术

    公开(公告)号：US08209488B2

    公开(公告)日：2012-06-26

    申请号：US12024248

    申请日：2008-02-01

    申请人： Ravi K. Arimilli ,  Balaram Sinharoy ,  William E. Speight ,  Lixin Zhang

    发明人： Ravi K. Arimilli ,  Balaram Sinharoy ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F13/00

    CPC分类号： G06F12/0862 ,  G06F12/0897 ,  G06F12/1027 ,  G06F2212/6026

    摘要： A technique for data prefetching using indirect addressing includes monitoring data pointer values, associated with an array, in an access stream to a memory. The technique determines whether a pattern exists in the data pointer values. A prefetch table is then populated with respective entries that correspond to respective array address/data pointer pairs based on a predicted pattern in the data pointer values. Respective data blocks (e.g., respective cache lines) are then prefetched (e.g., from the memory or another memory) based on the respective entries in the prefetch table.

    摘要翻译： 使用间接寻址的数据预取技术包括在到存储器的访问流中监视与阵列相关联的数据指针值。 该技术确定数据指针值中是否存在模式。 然后基于数据指针值中的预测模式，填充与各个阵列地址/数据指针对相对应的条目的预取表。 然后，基于预取表中的相应条目，预取（例如，从存储器或另一存储器）分别的数据块（例如，相应的高速缓存行）。

    Techniques for data prefetching using indirect addressing with offset
    83.
    发明授权
    Techniques for data prefetching using indirect addressing with offset 有权
    使用间接寻址偏移量进行数据预取的技术

    公开(公告)号：US08161264B2

    公开(公告)日：2012-04-17

    申请号：US12024246

    申请日：2008-02-01

    申请人： Ravi K. Arimilli ,  Balaram Sinharoy ,  William E. Speight ,  Lixin Zhang

    发明人： Ravi K. Arimilli ,  Balaram Sinharoy ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F13/00

    CPC分类号： G06F12/0862 ,  G06F12/1045 ,  G06F2212/6028

    摘要： A technique for performing data prefetching using indirect addressing includes determining a first memory address of a pointer associated with a data prefetch instruction. Content, that is included in a first data block (e.g., a first cache line) of a memory, at the first memory address is then fetched. An offset is then added to the content of the memory at the first memory address to provide a first offset memory address. A second memory address is then determined based on the first offset memory address. A second data block (e.g., a second cache line) that includes data at the second memory address is then fetched (e.g., from the memory or another memory). A data prefetch instruction may be indicated by a unique operational code (opcode), a unique extended opcode, or a field (including one or more bits) in an instruction.

    摘要翻译： 使用间接寻址执行数据预取的技术包括确定与数据预取指令相关联的指针的第一存储器地址。 然后取出包含在第一存储器地址的存储器的第一数据块（例如，第一高速缓存行）中的内容。 然后将偏移量添加到第一存储器地址处的存储器的内容以提供第一偏移存储器地址。 然后基于第一偏移存储器地址确定第二存储器地址。 包括第二存储器地址上的数据的第二数据块（例如，第二高速缓存行）然后被取出（例如，从存储器或另一个存储器）。 数据预取指令可以由指令中的唯一操作代码（操作码），唯一扩展操作码或字段（包括一个或多个位）来指示。

    Techniques for Dynamically Sharing a Fabric to Facilitate Off-Chip Communication for Multiple On-Chip Units
    84.
    发明申请
    Techniques for Dynamically Sharing a Fabric to Facilitate Off-Chip Communication for Multiple On-Chip Units 失效
    用于动态共享结构以促进多片式单元的片外通信的技术

    公开(公告)号：US20110296434A1

    公开(公告)日：2011-12-01

    申请号：US12786716

    申请日：2010-05-25

    申请人： Jian Li ,  William E. Speight ,  Lixin Zhang

    发明人： Jian Li ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F13/38 ,  G06F1/32 ,  G06F9/54

    CPC分类号： G06F1/3203 ,  G06F1/3253 ,  G06F9/5011 ,  Y02D10/151 ,  Y02D10/22

    摘要： A technique for sharing a fabric to facilitate off-chip communication for on-chip units includes dynamically assigning a first unit that implements a first communication protocol to a first portion of the fabric when private fabrics are indicated for the on-chip units. The technique also includes dynamically assigning a second unit that implements a second communication protocol to a second portion of the fabric when the private fabrics are indicated for the on-chip units. In this case, the first and second units are integrated in a same chip and the first and second protocols are different. The technique further includes dynamically assigning, based on off-chip traffic requirements of the first and second units, the first unit or the second unit to the first and second portions of the fabric when the private fabrics are not indicated for the on-chip units.

    摘要翻译： 一种用于共享一个结构以促进片上单元的片外通信的技术包括：当针对片上单元指示专用结构时，动态分配实现第一通信协议的第一单元到该结构的第一部分。 该技术还包括当为片上单元指示专用结构时，动态地将实现第二通信协议的第二单元分配给该结构的第二部分。 在这种情况下，第一和第二单元集成在相同的芯片中，并且第一和第二协议是不同的。 该技术还包括：当私有结构未被指示用于片上单元时，基于第一单元或第二单元的片外流量要求将第一单元或第二单元动态地分配给该结构的第一和第二部分 。

    Assigning Memory to On-Chip Coherence Domains
    85.
    发明申请
    Assigning Memory to On-Chip Coherence Domains 有权
    将内存分配给片上一致性域

    公开(公告)号：US20110296115A1

    公开(公告)日：2011-12-01

    申请号：US12787939

    申请日：2010-05-26

    申请人： William E. Speight ,  Lixin Zhang

    发明人： William E. Speight ,  Lixin Zhang

    IPC分类号： G06F12/08 ,  G06F12/00

    CPC分类号： G06F12/0831

    摘要： A mechanism is provided for assigning memory to on-chip cache coherence domains. The mechanism assigns caches within a processing unit to coherence domains. The mechanism then assigns chunks of memory to the coherence domains. The mechanism monitors applications running on cores within the processing unit to identify needs of the applications. The mechanism may then reassign memory chunks to the cache coherence domains based on the needs of the applications running in the coherence domains. When a memory controller receives the cache miss, the memory controller may look up the address in a lookup table that maps memory chunks to cache coherence domains. Snoop requests are sent to caches within the coherence domain. If a cache line is found in a cache within the coherence domain, the cache line is returned to the originating cache by the cache containing the cache line either directly or through the memory controller. If a cache line is not found within the coherence domain, the memory controller accesses the memory to retrieve the cache line.

    摘要翻译： 提供了一种用于将存储器分配给片上高速缓存一致性域的机制。 该机制将处理单元内的高速缓存分配给相干域。 该机制然后将大块内存分配给一致性域。 该机制监视在处理单元内的核心上运行的应用程序，以识别应用程序的需求。 然后，该机制可以基于在相干域中运行的应用的需要将存储器块重新分配给高速缓存一致性域。 当存储器控制器接收高速缓存未命中时，存储器控制器可以查找映射存储器块到高速缓存一致性域的查找表中的地址。 侦听请求被发送到连贯域内的缓存。 如果在相干域内的高速缓存中找到高速缓存行，则通过直接或通过存储器控制器的高速缓存行的高速缓存将高速缓存行返回到始发高速缓存。 如果在相干域内没有找到高速缓存行，则内存控制器访问内存以检索高速缓存行。

    Latency-Tolerant 3D On-Chip Memory Organization
    86.
    发明申请
    Latency-Tolerant 3D On-Chip Memory Organization 失效
    延迟容忍的3D片上存储器组织

    公开(公告)号：US20110296107A1

    公开(公告)日：2011-12-01

    申请号：US12787895

    申请日：2010-05-26

    申请人： Jian Li ,  William E. Speight ,  Lixin Zhang

    发明人： Jian Li ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F12/00 ,  G06F12/08

    CPC分类号： G06F12/0895 ,  G11C8/18

    摘要： A mechanism is provided within a 3D stacked memory organization to spread or stripe cache lines across multiple layers. In an example organization, a 128B cache line takes eight cycles on a 16B-wide bus. Each layer may provide 32B. The first layer uses the first two of the eight transfer cycles to send the first 32B. The next layer sends the next 32B using the next two cycles of the eight transfer cycles, and so forth. The mechanism provides a uniform memory access.

    摘要翻译： 在3D堆叠存储器组织内提供了一种机制，用于跨多层传播或条带化高速缓存行。 在一个示例组织中，128B高速缓存行在16B宽的总线上需要八个周期。 每层可提供32B。 第一层使用八个传输周期中的前两个发送第一个32B。 下一层使用八个传输周期的接下来的两个周期发送下一个32B，等等。 该机制提供了一个统一的内存访问。

    Mechanisms for Reducing DRAM Power Consumption
    87.
    发明申请
    Mechanisms for Reducing DRAM Power Consumption 失效
    降低DRAM功耗的机制

    公开(公告)号：US20110296097A1

    公开(公告)日：2011-12-01

    申请号：US12789019

    申请日：2010-05-27

    申请人： Elmootazbellah N. Elnozahy ,  Karthick Rajamani ,  William E. Speight ,  Lixin Zhang

    发明人： Elmootazbellah N. Elnozahy ,  Karthick Rajamani ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F12/00

    CPC分类号： G06F1/3275 ,  G11C11/406 ,  G11C11/4094 ,  G11C2211/4065 ,  G11C2211/4067 ,  Y02D10/13 ,  Y02D10/14

    摘要： Mechanisms are provided for inhibiting precharging of memory cells of a dynamic random access memory (DRAM) structure. The mechanisms receive a command for accessing memory cells of the DRAM structure. The mechanisms further determine, based on the command, if precharging the memory cells following accessing the memory cells is to be inhibited. Moreover, the mechanisms send, in response to the determination indicating that precharging the memory cells is to be inhibited, a command to blocking logic of the DRAM structure to block precharging of the memory cells following accessing the memory cells.

    摘要翻译： 提供用于禁止动态随机存取存储器（DRAM）结构的存储器单元的预充电的机制。 这些机制接收到用于访问DRAM结构的存储单元的命令。 这些机制基于该命令进一步确定如果禁止在访问存储器单元之后对存储单元进行预充电。 此外，机构响应于指示要禁止对存储器单元进行预充电的确定，发送阻止DRAM结构的逻辑以阻止访问存储器单元之后的存储器单元的预充电的命令。

    Dynamic adjustment of prefetch stream priority
    89.
    发明授权
    Dynamic adjustment of prefetch stream priority 有权
    预取流优先级的动态调整

    公开(公告)号：US07958316B2

    公开(公告)日：2011-06-07

    申请号：US12024411

    申请日：2008-02-01

    申请人： William E. Speight ,  Lixin Zhang

    发明人： William E. Speight ,  Lixin Zhang

    IPC分类号： G06F12/12 ,  G06F5/12

    CPC分类号： G06F12/0862 ,  G06F2212/1041 ,  G06F2212/6024

    摘要： A method, processor, and data processing system for dynamically adjusting a prefetch stream priority based on the consumption rate of the data by the processor. The method includes a prefetch engine issuing a prefetch request of a first prefetch stream to fetch one or more data from the memory subsystem. The first prefetch stream has a first assigned priority that determines a relative order for scheduling prefetch requests of the first prefetch stream relative to other prefetch requests of other prefetch streams. Based on the receipt of a processor demand for the data before the data returns to the cache or return of the data along time before the receiving the processor demand, logic of the prefetch engine dynamically changes the first assigned priority to a second higher or lower priority, which priority is subsequently utilized to schedule and issue a next prefetch request of the first prefetch stream.

    摘要翻译： 一种用于基于处理器的数据的消耗速率动态地调整预取流优先级的方法，处理器和数据处理系统。 该方法包括预取引擎，其发出第一预取流的预取请求以从存储器子系统获取一个或多个数据。 第一预取流具有第一分配的优先级，其相对于其他预取流的其他预取请求确定第一预取流的调度预取请求的相对顺序。 基于在数据返回到高速缓存之前对数据的接收处理器需求，或者在接收到处理器需求之前的时间返回数据，预取引擎的逻辑动态地将第一分配的优先级改变为第二较高或更低的优先级 随后利用该优先级来调度和发出第一预取流的下一个预取请求。

    Branch target address cache
    90.
    发明授权
    Branch target address cache 失效
    分支目标地址缓存

    公开(公告)号：US07783870B2

    公开(公告)日：2010-08-24

    申请号：US11837893

    申请日：2007-08-13

    申请人： David S. Levitan ,  William E. Speight ,  Lixin Zhang

    发明人： David S. Levitan ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F9/38 ,  G06F9/32

    CPC分类号： G06F9/3804 ,  G06F9/3844

    摘要： A processor includes an execution unit and instruction sequencing logic that fetches instructions from a memory system for execution. The instruction sequencing logic includes branch logic that outputs predicted branch target addresses for use as instruction fetch addresses. The branch logic includes a level one branch target address cache (BTAC) and a level two BTAC each having a respective plurality of entries each associating at least a tag with a predicted branch target address. The branch logic accesses the level one and level two BTACs in parallel with a tag portion of a first instruction fetch address to obtain a first predicted branch target address from the level one BTAC for use as a second instruction fetch address in a first processor clock cycle and a second predicted branch target address from the level two BTAC for use as a third instruction fetch address in a later second processor clock cycle.

    摘要翻译： 处理器包括执行单元和从存储器系统执行指令的指令排序逻辑。 指令排序逻辑包括分支逻辑，该分支逻辑输出用作指令获取地址的预测分支目标地址。 分支逻辑包括一级分支目标地址高速缓存（BTAC）和二级BTAC，每级具有相应的多个条目，每个条目将至少一个标签与预测的分支目标地址相关联。 分支逻辑与第一指令获取地址的标签部分并行地访问一级和二级BTAC以从第一级BTAC获得第一预测分支目标地址，以在第一处理器时钟周期中用作第二指令获取地址 以及来自第二级BTAC的第二预测分支目标地址，以在随后的第二处理器时钟周期中用作第三指令提取地址。