公开(公告)号：US6043544A

公开(公告)日：2000-03-28

申请号：US140202

申请日：1998-08-26

申请人： Mark W. Michael ,  Robert Dawson

发明人： Mark W. Michael ,  Robert Dawson

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L29/76

CPC分类号： H01L21/28035 ,  H01L21/823842

摘要： A semiconductor fabrication process is presented which optimizes the position of impurities within a gate conductor a the source/drain straddling the gate conductor. Optimal positioning is achieved by using separate implants of different energies depending upon whether the gate conductor connotes a PMOS or NMOS transistor. A layer of polysilicon used to form the gate conductor is doped before patterning so that the source and drain regions are protected. A low energy implant is performed when implanting a fast diffuser such as boron, and a high energy implant is performed when implanting a slow diffuser like arsenic. This enables optimum positioning of the impurities throughout the gate conductor cross-section after heat cycles are applied. Fast diffusers are initially placed far from the bottom surface of the polysilicon, and diffuse near the bottom surface of the polysilicon when heat is applied. Slow diffusers are initially placed closer to the bottom surface of the polysilicon, since they do not diffuse as readily. The source and drain regions are implanted using a very low energy implant, separately from the polysilicon implants, to produce a desirable shallow source and drain region within the semiconductor substrate.

摘要翻译： 提出了一种半导体制造工艺，其优化栅极导体内杂质的位置，栅极导体中跨越栅极导体的源极/漏极。 通过使用不同能量的单独注入来取决于栅极导体是指PMOS还是NMOS晶体管来实现最佳定位。 用于形成栅极导体的多晶硅层在图案化之前被掺杂，使得源极和漏极区域受到保护。 当植入诸如硼的快速扩散器时执行低能量注入，并且当植入像砷这样的慢扩散器时执行高能量注入。 这使得在施加热循环之后，杂质在整个栅极导体横截面中的最佳定位。 最初放置快速扩散器远离多晶硅的底表面，并在加热时在多晶硅的底表面附近扩散。 缓慢扩散器最初放置得更靠近多晶硅的底表面，因为它们不会容易地扩散。 使用与多晶硅植入物分开的非常低能量的注入来注入源极区和漏极区，以在半导体衬底内产生期望的浅源极和漏极区。

公开(公告)号：US5963803A

公开(公告)日：1999-10-05

申请号：US17254

申请日：1998-02-02

申请人： Robert Dawson ,  Mark W. Michael ,  Charles E. May

发明人： Robert Dawson ,  Mark W. Michael ,  Charles E. May

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L27/02

CPC分类号： H01L21/82385 ,  H01L21/823864 ,  H01L27/0922

摘要： A method of making N-channel and P-channel IGFETs with different gate thicknesses and spacer widths is disclosed. The method includes providing a semiconductor substrate with a first active region of a first conductivity type and a second active region of a second conductivity type, forming a first gate over the first active region and a second gate over the second active region, wherein the second gate has a substantially greater thickness than the first gate, forming first spacers in close proximity to opposing sidewalls of the first gate and second spacers in close proximity to opposing sidewalls of the second gate, wherein the second spacers have a substantially greater width than the first spacers due to the second gate having a substantially greater thickness than the first gate, and forming a first source and a first drain of the second conductivity type in the first active region and a second source and a second drain of the first conductivity type in the second active region. Preferably, the N-channel device is formed in the first active region, the P-channel device is formed in the second active region, and the N-channel and P-channel devices include lightly and heavily doped source and drain regions. In this manner, the relatively thick gate for the P-channel device reduces boron penetration, and the relatively wide spacers for the P-channel device offset the rapid diffusion of boron in the heavily doped source and drain regions of the P-channel device during high temperature processing so that the lightly doped source and drain regions for the N-channel and P-channel devices have the desired sizes.

摘要翻译： 公开了一种制造具有不同栅极厚度和间隔物宽度的N沟道和P沟道IGFET的方法。 该方法包括提供具有第一导电类型的第一有源区和第二导电类型的第二有源区的半导体衬底，在第一有源区上形成第一栅极，在第二有源区上形成第二栅极，其中第二有源区 栅极具有比第一栅极大得多的厚度，在第二栅极的相对侧壁附近形成第一间隔物，其紧邻第一栅极的相对侧壁和第二间隔物，其中第二间隔物具有比第一栅极大得多的宽度 由于第二栅极具有比第一栅极大得多的厚度的间隔物，以及在第一有源区中形成第二导电类型的第一源极和第一漏极，以及在第一有源区中形成第一导电类型的第二源极和第二漏极 第二活跃区域。 优选地，N沟道器件形成在第一有源区中，P沟道器件形成在第二有源区中，并且N沟道和P沟道器件包括轻掺杂和重掺杂的源极和漏极区。 以这种方式，用于P沟道器件的相对较厚的栅极减少硼渗透，并且用于P沟道器件的相对较宽的间隔物抵消P沟道器件的重掺杂源极和漏极区域中硼的快速扩散， 高温处理使得用于N沟道和P沟道器件的轻掺杂源极和漏极区域具有期望的尺寸。

公开(公告)号：US6054356A

公开(公告)日：2000-04-25

申请号：US761332

申请日：1996-12-10

申请人： Robert Dawson ,  Mark W. Michael ,  Fred N. Hause

发明人： Robert Dawson ,  Mark W. Michael ,  Fred N. Hause

IPC分类号： H01L21/266 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66598 ,  H01L21/266 ,  H01L29/6659 ,  H01L29/7833

摘要： A transistor is provided with a gradually increasing source and drain arsenic doping profile in a lateral direction from the gate conductor sidewall surfaces. The very smooth doping profile ensures small electric fields at the channel-drain interface for the benefit of reducing hot-carrier effects. Such a doping profile may be achieved by performing the ion implantation through a non-conformal layer of spin-on glass. By controlling the viscosity of the SOG and its deposition speed, different meniscus shapes may be formed. The doping profile of the arsenic in the source and drain regions follows the profile of the upper surface of the SOG. Arsenic is advantageously used for both the lightly doped and heavily doped regions of the source/drain junctions. Arsenic has lower mobility compared to phosphorus and is better at maintaining its original doping profile in heating of the device during further processing. Too much alteration in the original doping profile over time may change the device characteristics beyond acceptable levels.

摘要翻译： 晶体管在栅极导体侧壁表面的横向上设置有逐渐增加的源极和漏极砷掺杂分布。 非常平滑的掺杂分布确保了通道 - 漏极界面的小电场，有利于减少热载流子效应。 这种掺杂分布可以通过通过旋涂玻璃的非保形层进行离子注入来实现。 通过控制SOG的粘度及其沉积速度，可以形成不同的弯液面形状。 源极和漏极区域中的砷的掺杂分布遵循SOG的上表面的轮廓。 砷有利地用于源极/漏极结的轻掺杂区域和重掺杂区域。 砷与磷相比具有较低的迁移率，并且在进一步加工期间更好地保持其在加热装置中的原始掺杂特性。 随着时间的推移，原始掺杂特性的变化可能会将器件特性改变为可接受的水平。

公开(公告)号：US6027859A

公开(公告)日：2000-02-22

申请号：US992234

申请日：1997-12-17

申请人： Robert Dawson ,  Mark W. Michael ,  Fred Hause

发明人： Robert Dawson ,  Mark W. Michael ,  Fred Hause

IPC分类号： G03F7/20

CPC分类号： G03F7/70633 ,  G03F7/70475

摘要： The present invention generally provides a semiconductor substrate having an extended test structure and a method of fabricating such a substrate. A method of forming an extended test structure on a semiconductor substrate, consistent with one embodiment of the invention, includes forming a first test structure pattern over a first portion of the substrate and forming a second test structure pattern of the second portion of the substrate which partially overlaps the first portion of the substrate such that the first test structure pattern and the second test structure overlap. The first test structure pattern may be formed using, for example, reticle and a second test structure pattern may be formed using the same reticle. The first and second test structure patterns may, for example, be formed in a scribe line of the substrate.

摘要翻译： 本发明通常提供具有扩展测试结构的半导体衬底和制造这种衬底的方法。 根据本发明的一个实施例，在半导体衬底上形成扩展测试结构的方法包括在衬底的第一部分上形成第一测试结构图案，并形成衬底的第二部分的第二测试结构图案， 部分地与衬底的第一部分重叠，使得第一测试结构图案和第二测试结构重叠。 可以使用例如掩模版形成第一测试结构图案，并且可以使用相同的掩模版形成第二测试结构图案。 第一和第二测试结构图案可以例如形成在基板的划线中。

公开(公告)号：US5851889A

公开(公告)日：1998-12-22

申请号：US792714

申请日：1997-01-30

申请人： Mark W. Michael ,  Robert Dawson

发明人： Mark W. Michael ,  Robert Dawson

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/28035 ,  H01L21/823842

摘要： A semiconductor fabrication process is presented which optimizes the position of impurities within a gate conductor a the source/drain straddling the gate conductor. Optimal positioned is achieved by using separate implants of different energies depending upon whether the gate conductor connotes a PMOS or NMOS transistor. A layer of polysilicon used to form the gate conductor is doped before patterning so that the source and drain regions are protected. A low energy implant is performed when implanting a fast diffuser such as boron, and a high energy implant is performed when implanting a slow diffuser like arsenic. This enables optimum positioning of the impurities throughout the gate conductor cross-section after heat cycles are applied. Fast diffusers are initially placed far from the bottom surface of the polysilicon, and diffuse near the bottom surface of the polysilicon when heat is applied. Slow diffusers are initially placed closer to the bottom surface of the polysilicon, since they do not diffuse as readily. The source and drain regions are implanted using a very low energy implant, separately from the polysilicon implants, to produce a desirable shallow source and drain region within the semiconductor substrate.

摘要翻译： 提出了一种半导体制造工艺，其优化栅极导体内杂质的位置，栅极导体中跨越栅极导体的源极/漏极。 取决于栅极导体是指PMOS还是NMOS晶体管，通过使用不同能量的单独注入来实现最佳定位。 用于形成栅极导体的多晶硅层在图案化之前被掺杂，使得源极和漏极区域受到保护。 当植入诸如硼的快速扩散器时执行低能量注入，并且当植入像砷这样的慢扩散器时执行高能量注入。 这使得在施加热循环之后，杂质在整个栅极导体横截面中的最佳定位。 最初放置快速扩散器远离多晶硅的底表面，并在加热时在多晶硅的底表面附近扩散。 缓慢扩散器最初放置得更靠近多晶硅的底表面，因为它们不会容易地扩散。 使用与多晶硅植入物分开的非常低能量的注入来注入源极区和漏极区，以在半导体衬底内产生期望的浅源极和漏极区。

公开(公告)号：US07670938B2

公开(公告)日：2010-03-02

申请号：US11381219

申请日：2006-05-02

申请人： David D. Wu ,  Mark W. Michael

发明人： David D. Wu ,  Mark W. Michael

IPC分类号： H01L21/44

CPC分类号： H01L21/76819 ,  H01L21/76802 ,  H01L21/76834 ,  H01L29/7843

摘要： The present invention is directed to methods of forming contact openings. In one illustrative embodiment, the method includes forming a feature above a semiconducting substrate, forming a layer stack comprised of a plurality of layers of material above the feature, the layer stack having an original height, reducing the original height of the layer stack to thereby define a reduced height layer stack above the feature, forming an opening in the reduced height layer stack for a conductive member that will be electrically coupled to the feature and forming the conductive member in the opening in the reduced height layer stack.

摘要翻译： 本发明涉及形成接触开口的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成特征，形成由特征上方的多层材料构成的层叠层，层堆叠具有原始高度，从而降低层堆叠的原始高度 在所述特征之上限定减小的高度层堆叠，在所述减小的高度层堆叠中形成用于导电构件的开口，所述导电构件将电耦合到所述特征并且在所述还原高度层堆叠中的所述开口中形成所述导电构件。

公开(公告)号：US20090090969A1

公开(公告)日：2009-04-09

申请号：US11867743

申请日：2007-10-05

申请人： Ruigang Li ,  Jingrong Zhou ,  David Donggang Wu ,  Zhonghai Shi ,  James F. Buller ,  Mark W. Michael ,  Donna Michael ,  Akif Sultan ,  Fred Hause

发明人： Ruigang Li ,  Jingrong Zhou ,  David Donggang Wu ,  Zhonghai Shi ,  James F. Buller ,  Mark W. Michael ,  Donna Michael ,  Akif Sultan ,  Fred Hause

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A first bias charge is provided to first bias region at a first level of an electronic device, the first bias region directly underlying a first transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the first transistor is based upon the first bias charge. A second bias charge is provided to second bias region at the first level of an electronic device, the second bias region directly underlying a second transistor having a channel region at a second level that is electrically isolated from the first bias region. A voltage threshold of the second transistor is based upon the second bias charge.

摘要翻译： 第一偏置电荷被提供给电子器件的第一电平处的第一偏置区域，直接位于第一晶体管下方的第一偏置区域具有与第一偏置区域电隔离的第二电平的沟道区域。 第一晶体管的电压阈值基于第一偏置电荷。 第二偏置电荷被提供给电子器件的第一电平处的第二偏置区域，第二偏置区域直接位于具有与第一偏置区域电隔离的第二电平的沟道区域的第二晶体管的正下方。 第二晶体管的电压阈值基于第二偏置电荷。

公开(公告)号：US20080104550A1

公开(公告)日：2008-05-01

申请号：US11537390

申请日：2006-09-29

申请人： Akif Sultan ,  Jian Chen ,  Mark W. Michael ,  Jingrong R. Zhou

发明人： Akif Sultan ,  Jian Chen ,  Mark W. Michael ,  Jingrong R. Zhou

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A method includes receiving design data associated with an integrated circuit device. The integrated circuit device includes a first element having a corner defined therein and a second element overlapping the first element. A dimension specified for the first element in the design data is adjusted based on a distance between the second element and the corner. The integrated circuit device is simulated based on the adjusted dimension.

摘要翻译： 一种方法包括接收与集成电路装置相关联的设计数据。 集成电路装置包括具有限定在其中的角部的第一元件和与第一元件重叠的第二元件。 基于第二元件和拐角之间的距离来调整为设计数据中的第一元件指定的尺寸。 基于经调整的尺寸模拟集成电路器件。

公开(公告)号：US20080003789A1

公开(公告)日：2008-01-03

申请号：US11428022

申请日：2006-06-30

申请人： Jian Chen ,  Mark W. Michael

发明人： Jian Chen ,  Mark W. Michael

IPC分类号： H01L21/3205

CPC分类号： H01L21/823418 ,  H01L21/823814 ,  H01L29/7843 ,  H01L29/7848

摘要： A method includes forming a plurality of functional features on a semiconductor layer in a first region. A non-functional feature corresponding to the functional feature is formed adjacent at least one of the functional features disposed on a periphery of the region. A stress-inducing layer is formed over at least a portion of the functional features and the non-functional feature. A device includes a semiconductor layer, a first dummy gate electrode, and a stress-inducing layer. The plurality of transistor gate electrodes is formed above the semiconductor layer. The plurality includes at least a first end gate electrode, a second end gate electrode, and at least one interior gate electrode. The first dummy gate electrode is disposed proximate the first end gate electrode. The stress-inducing layer is disposed over at least a portion of the plurality of transistor gate electrodes and the first dummy gate electrode.

摘要翻译： 一种方法包括在第一区域中的半导体层上形成多个功能特征。 相邻于功能特征的非功能特征形成在邻近设置在区域周边的功能特征中的至少一个功能特征。 在功能特征和非功能特征的至少一部分上形成应力诱导层。 一种器件包括半导体层，第一伪栅电极和应力诱导层。 多个晶体管栅电极形成在半导体层的上方。 多个至少包括第一端栅极电极，第二端栅极电极和至少一个内部栅极电极。 第一虚拟栅电极设置在第一端栅电极附近。 应力感应层设置在多个晶体管栅极电极和第一虚拟栅电极的至少一部分上。

公开(公告)号：US5869378A

公开(公告)日：1999-02-09

申请号：US637980

申请日：1996-04-26

申请人： Mark W. Michael

发明人： Mark W. Michael

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/28123 ,  H01L29/7833

摘要： A method of manufacturing an integrated circuit so as to reduce overlap between an LDD region and a gate electrode is disclosed. The method includes forming a gate electrode on a gate insulator on a semiconductor substrate, implanting a lightly-doped drain (LDD) region in the substrate using the gate electrode as a mask, removing a lateral portion of the gate electrode after implanting the LDD region, and then laterally diffusing the LDD region into the substrate such that a lateral edge of the LDD region is substantially aligned with a lateral edge of the gate electrode. Preferably, the lateral portion of the gate electrode is removed using an isotropic etch. The method further includes forming a spacer adjacent to an edge of the gate electrode after removing the lateral portion, and then implanting a heavily-doped region using the spacer and gate electrode as an implant mask.

摘要翻译： 公开了一种制造集成电路以减少LDD区和栅电极之间的重叠的方法。 该方法包括在半导体衬底上的栅极绝缘体上形成栅电极，使用栅电极作为掩模将轻掺杂漏极（LDD）区域注入到衬底中，在注入LDD区之后去除栅电极的侧向部分 ，然后将LDD区域横向扩散到衬底中，使得LDD区域的横向边缘基本上与栅电极的侧边缘对齐。 优选地，使用各向同性蚀刻去除栅电极的侧向部分。 该方法还包括在去除侧面部分之后形成邻近栅电极的边缘的间隔物，然后使用间隔物和栅极电极注入重掺杂区域作为植入物掩模。