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260 条记录 (耗时 0.039 秒)

    Band gap modulated optical sensor
    82.
    发明授权
    Band gap modulated optical sensor 有权
    带隙调制光传感器

    公开(公告)号：US07888266B2

    公开(公告)日：2011-02-15

    申请号：US12146560

    申请日：2008-06-26

    申请人： Kangguo Cheng ,  Toshiharu Furukawa ,  Robert Robison ,  William R. Tonti

    发明人： Kangguo Cheng ,  Toshiharu Furukawa ,  Robert Robison ,  William R. Tonti

    IPC分类号： H01L21/311

    CPC分类号： H01L27/1461 ,  H01L27/14645 ,  H01L27/14689

    摘要： A complementary metal-oxide-semiconductor (CMOS) optical sensor structure includes a pixel containing a charge collection well of a same semiconductor material as a semiconductor layer in a semiconductor substrate and at least another pixel containing another charge collection well of a different semiconductor material than the material of the semiconductor layer. The charge collections wells have different band gaps, and consequently, generate charge carriers in response to light having different wavelengths. The CMOS sensor structure thus includes at least two pixels responding to light of different wavelengths, enabling wavelength-sensitive, or color-sensitive, capture of an optical data.

    摘要翻译： 互补金属氧化物半导体（CMOS）光学传感器结构包括含有与半导体衬底中的半导体层相同的半导体材料的电荷收集阱的像素，以及包含不同半导体材料的另一电荷收集阱的至少另一个像素 半导体层的材料。 电荷收集阱具有不同的带隙，因此响应于具有不同波长的光而产生电荷载流子。 因此，CMOS传感器结构包括响应于不同波长的光的至少两个像素，使得能够对光学数据进行波长敏感或颜色敏感的捕获。

    FINFET FUSE WITH ENHANCED CURRENT CROWDING
    86.
    发明申请
    FINFET FUSE WITH ENHANCED CURRENT CROWDING 失效
    FINFET保险丝与增强电流冲击

    公开(公告)号：US20120187528A1

    公开(公告)日：2012-07-26

    申请号：US13011215

    申请日：2011-01-21

    申请人： Kangguo Cheng ,  Louis C. Hsu ,  William R. Tonti ,  Chih-Chao Yang

    发明人： Kangguo Cheng ,  Louis C. Hsu ,  William R. Tonti ,  Chih-Chao Yang

    IPC分类号： H01L23/525 ,  H01L21/44

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

    摘要： A method forms an eFuse structure that has a pair of adjacent semiconducting fins projecting from the planar surface of a substrate (in a direction perpendicular to the planar surface). The fins have planar sidewalls (perpendicular to the planar surface of the substrate) and planar tops (parallel to the planar surface of the substrate). The tops are positioned at distal ends of the fins relative to the substrate. An insulating layer covers the tops and the sidewalls of the fins and covers an intervening substrate portion of the planar surface of the substrate located between the fins. A metal layer covers the insulating layer. A pair of conductive contacts are connected to the metal layer at locations where the metal layer is adjacent the top of the fins.

    摘要翻译： 一种方法形成eFuse结构，其具有从衬底的平面（垂直于平面的方向）突出的一对相邻半导体翅片。 散热片具有平面侧壁（垂直于基板的平面）和平面顶部（平行于基板的平面）。 顶部相对于基底定位在翅片的远端。 绝缘层覆盖翅片的顶部和侧壁，并且覆盖位于翅片之间的衬底的平面表面的中间衬底部分。 金属层覆盖绝缘层。 在金属层邻近翅片顶部的位置处，一对导电触头连接到金属层。

    FIELD EFFECT TRANSISTORS WITH LOW K SIDEWALL SPACERS AND METHODS OF FABRICATING SAME
    87.
    发明申请
    FIELD EFFECT TRANSISTORS WITH LOW K SIDEWALL SPACERS AND METHODS OF FABRICATING SAME 失效
    具有低K面积间距的场效应晶体管及其制造方法

    公开(公告)号：US20120126342A1

    公开(公告)日：2012-05-24

    申请号：US12948805

    申请日：2010-11-18

    申请人： Kangguo Cheng ,  Louis Lu-Chen Hsu ,  William R. Tonti

    发明人： Kangguo Cheng ,  Louis Lu-Chen Hsu ,  William R. Tonti

    IPC分类号： H01L29/772 ,  H01L21/336

    CPC分类号： H01L29/4983 ,  H01L21/26586 ,  H01L21/268 ,  H01L29/665

    摘要： Field effect transistors and method for forming filed effect transistors. The field effect transistors including: a gate dielectric on a channel region in a semiconductor substrate; a gate electrode on the gate dielectric; respective source/drains in the substrate on opposite sides of the channel region; sidewall spacers on opposite sides of the gate electrode proximate to the source/drains; and wherein the sidewall spacers comprise a material having a dielectric constant lower than that of silicon dioxide and capable of absorbing laser radiation.

    摘要翻译： 场效应晶体管和形成场效应晶体管的方法。 场效应晶体管包括：半导体衬底中的沟道区上的栅极电介质; 栅电极上的栅电极; 在沟道区域的相对侧上的衬底中的相应源极/漏极; 靠近源极/漏极的栅电极的相对侧上的侧壁间隔物; 并且其中所述侧壁间隔物包括介电常数低于二氧化硅的介电常数且能够吸收激光辐射的材料。

    PROGRAMMABLE ANTI-FUSE STRUCTURES WITH CONDUCTIVE MATERIAL ISLANDS
    89.
    发明申请
    PROGRAMMABLE ANTI-FUSE STRUCTURES WITH CONDUCTIVE MATERIAL ISLANDS 失效
    具有导电材料岛的可编程防结构

    公开(公告)号：US20110254121A1

    公开(公告)日：2011-10-20

    申请号：US12761780

    申请日：2010-04-16

    申请人： Kangguo Cheng ,  Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

    发明人： Kangguo Cheng ,  Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

    IPC分类号： H01L23/525 ,  H01L21/768 ,  G06F17/50

    CPC分类号： H01L23/5252 ,  G06F17/505 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Voltage programmable anti-fuse structures and methods are provided that include at least one conductive material island atop a dielectric surface that is located between two adjacent conductive features. In one embodiment, the anti-fuse structure includes a dielectric material having at least two adjacent conductive features embedded therein. At least one conductive material island is located on an upper surface of the dielectric material that is located between the at least two adjacent conductive features. A dielectric capping layer is located on exposed surfaces of the dielectric material, the at least one conductive material island and the at least two adjacent conductive features. When the anti-fuse structure is in a programmed state, a dielectric breakdown path is present in the dielectric material that is located beneath the at least one conductive material island which conducts electrical current to electrically couple the two adjacent conductive features.

    摘要翻译： 提供了电压可编程的抗熔丝结构和方法，其包括位于介于两个相邻导电特征之间的电介质表面上的至少一个导电材料岛。 在一个实施例中，反熔丝结构包括具有嵌入其中的至少两个相邻导电特征的电介质材料。 至少一个导电材料岛位于介电材料的位于至少两个相邻导电特征之间的上表面上。 电介质覆盖层位于电介质材料的暴露表面上，至少一个导电材料岛和至少两个相邻的导电特征。 当反熔丝结构处于编程状态时，介电击穿路径存在于介电材料中，介电材料位于至少一个导电材料岛之下，该导电材料岛传导电流以电耦合两个相邻导电特征。