公开(公告)号：US20220208556A1

公开(公告)日：2022-06-30

申请号：US17355955

申请日：2021-06-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Roshan Jayakhar TIRUKKONDA ,  Senaka KANAKAMEDALA ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Monica TITUS

IPC: H01L21/311 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11597 ,  H01L27/11592 ,  H01L21/768

Abstract: An alternating stack of first material layers and second material layers can be formed over a semiconductor material layer. A patterning film is formed over the alternating stack, and openings are formed through the patterning film. Via openings are formed through the alternating stack at least to a top surface of the semiconductor material layer by performing a first anisotropic etch process that transfers a pattern of the openings in the patterning film. A cladding liner can be formed on a top surface of the patterning film and sidewalls of the openings in the pattering film. The via openings can be vertically extended through the semiconductor material layer at least to a bottom surface of the semiconductor material layer by performing a second anisotropic etch process employing the cladding liner as an etch mask.

公开(公告)号：US20220139949A1

公开(公告)日：2022-05-05

申请号：US17085735

申请日：2020-10-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Adarsh RAJASHEKHAR

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/522 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  G11C8/14

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Each electrically conductive layer within a subset of the electrically conductive layers includes a respective first metal layer containing an elemental metal and a respective first metal silicide layer containing a metal silicide of the elemental metal. Memory openings vertically extend through the alternating stack. Memory opening fill structures located within the memory openings can include a respective memory film and a respective vertical semiconductor channel.

公开(公告)号：US20210375848A1

公开(公告)日：2021-12-02

申请号：US16886221

申请日：2020-05-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei ZHOU ,  Raghuveer S. MAKALA ,  Rahul SHARANGPANI ,  Adarsh RAJASHEKHAR

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: Multiple bonded units are provided, each of which includes a respective front-side die and a backside die. The two dies in each bonded unit may be a memory die and a logic die configured to control operation of memory elements in the memory die. Alternatively, the two dies may be memory dies. The multiple bonded units can be attached such that front-side external bonding pads have physically exposed surfaces that face upward and backside external bonding pads of each bonded unit have physically exposed surfaces that face downward. A first set of bonding wires can connect a respective pair of front-side external bonding pads, and a second set of bonding wires can connect a respective pair of backside external bonding pads.

公开(公告)号：US20210358942A1

公开(公告)日：2021-11-18

申请号：US16877328

申请日：2020-05-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh RAJASHEKHAR ,  Rahul SHARANGPANI ,  Raghuveer S. MAKALA ,  Fei ZHOU ,  Yanli ZHANG

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11543 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11519

Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening through the alternating stack, forming lateral recesses at levels of the sacrificial material layers around the memory opening, forming a vertical stack of discrete clam-shaped semiconductor liners in the lateral recesses, replacing the vertical stack of discrete clam-shaped semiconductor liners with a vertical stack of inner clam-shaped metallic liners, forming a vertical stack of discrete charge storage elements on the vertical sack of inner clam-shaped metallic liners, forming a tunneling dielectric layer and a vertical semiconductor channel over the vertical stack of discrete charge storage elements and the vertical stack of inner clam-shaped metallic liners, and replacing each of the sacrificial material layers with an electrically conductive layer.

公开(公告)号：US20210358931A1

公开(公告)日：2021-11-18

申请号：US16876877

申请日：2020-05-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. MAKALA ,  Yanli ZHANG ,  Fei ZHOU ,  Rahul SHARANGPANI ,  Adarsh RAJASHEKHAR ,  Seung-Yeul YANG

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11597 ,  H01L27/11539

Abstract: A memory opening or a line trench is formed through an alternating stack of insulating layers and sacrificial material layers. A memory opening fill structure or a memory stack assembly is formed, which includes a vertical stack of discrete intermediate metallic electrodes formed on sidewalls of the sacrificial material layers, a gate dielectric layer, and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers, and a combination of a ferroelectric dielectric layer and an electrically conductive layer within each of the backside recesses. The electrically conductive layer is laterally spaced from a respective one of the discrete intermediate metallic electrodes by the ferroelectric dielectric layer. Ferroelectric-metal-insulator memory elements are formed around the vertical semiconductor channel.

公开(公告)号：US20210327890A1

公开(公告)日：2021-10-21

申请号：US16849664

申请日：2020-04-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. MAKALA ,  Senaka KANAKAMEDALA ,  Fei ZHOU ,  Yao-Sheng LEE

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L23/538 ,  H01L29/423

Abstract: An alternating stack of insulating layers and spacer material layers can be formed over a substrate. The spacer material layers may be formed as, or may be subsequently replaced with, electrically conductive layers. A memory opening can be formed through the alternating stack, and annular lateral recesses are formed at levels of the insulating layers. Metal portions are formed in the annular lateral recesses, and a semiconductor material layer is deposited over the metal portions. Metal-semiconductor alloy portions are formed by performing an anneal process, and are subsequently removed by performing a selective etch process. Remaining portions of the semiconductor material layer include a vertical stack of semiconductor material portions, which may be optionally converted, partly or fully, into silicon nitride material portions. The semiconductor material portions and/or the silicon nitride material portions can be employed as discrete charge storage elements.

公开(公告)号：US20210265372A1

公开(公告)日：2021-08-26

申请号：US16801456

申请日：2020-02-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Senaka KANAKAMEDALA ,  Raghuveer S. MAKALA ,  Yao-Sheng LEE

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  H01L23/532

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and word lines that are made of molybdenum layers located over a substrate, and memory stack structures extending through each layer in the alternating stack. Each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Each memory film includes a vertical stack of discrete tubular dielectric metal oxide spacers in contact with a respective one of the molybdenum layers, a continuous silicon oxide blocking dielectric layer contacting an inner sidewall of each of the tubular dielectric metal oxide spacers, a vertical stack of charge storage material portions, and a tunneling dielectric layer contacting each of the charge storage material portions and the vertical semiconductor channel.

公开(公告)号：US20210082865A1

公开(公告)日：2021-03-18

申请号：US17106831

申请日：2020-11-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ashish BARASKAR ,  Raghuveer S. MAKALA ,  Peter RABKIN

IPC: H01L23/00 ,  H01L21/762 ,  H01L25/00 ,  H01L25/18 ,  H01L21/683

Abstract: A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a first single crystalline semiconductor layer, and memory stack structures extending through the alternating stack and containing respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die includes a peripheral circuitry. Substrates employed to provide the memory die and the support die can be reused by replacing one of the substrates with an alternative low-cost substrate that provides structural support to the bonded assembly.

公开(公告)号：US20210028149A1

公开(公告)日：2021-01-28

申请号：US16523029

申请日：2019-07-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. MAKALA ,  Johann ALSMEIER

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: A method of forming a bonded assembly includes providing a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads that are electrically connected to a respective node of the first semiconductor devices, forming a first oxidation barrier layer on physically exposed surfaces of the first bonding pads, providing a second semiconductor die containing a second substrate, second semiconductor devices, and second bonding pads that are electrically connected to a respective node of the second semiconductor devices, and bonding the second bonding pads to the first bonding pads with at least the first oxidation barrier layer located between the respective first and second bonding pads.

公开(公告)号：US20210028136A1

公开(公告)日：2021-01-28

申请号：US16851839

申请日：2020-04-17

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely SAID ,  Senaka KANAKAMEDALA ,  Raghuveer S. MAKALA

IPC: H01L23/00 ,  H01L23/522 ,  H01L25/065

Abstract: At least one polymer material may be employed to facilitate bonding between the semiconductor dies. Plasma treatment, formation of a blended polymer, or formation of polymer hairs may be employed to enhance bonding. Alternatively, air gaps can be formed by subsequently removing the polymer material to reduce capacitive coupling between adjacent bonding pads.