公开(公告)号：US20230127474A1

公开(公告)日：2023-04-27

申请号：US17892190

申请日：2022-08-22

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hitoshi KUNITAKE ,  Ryunosuke HONDA ,  Tomoaki ATSUMI

IPC: H10B12/00 ,  G11C11/405 ,  G11C11/4074 ,  H01L29/66

Abstract: A semiconductor device capable of obtaining the threshold voltage of a transistor is provided. The semiconductor device includes a first transistor, a first capacitor, a first output terminal, a first switch, and a second switch. A gate and a source of the first transistor are electrically connected to each other. A first terminal of the first capacitor is electrically connected to the source. A second terminal and the first output terminal of the first capacitor are electrically connected to a back gate of the first transistor. The first switch controls input of a first voltage to the back gate. A second voltage is input to a drain of the first transistor. The second switch controls input of a third voltage to the source.

公开(公告)号：US20220328487A1

公开(公告)日：2022-10-13

申请号：US17634270

申请日：2020-08-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hajime KIMURA ,  Tatsuya ONUKI ,  Hitoshi KUNITAKE

IPC: H01L27/108

Abstract: A semiconductor device with a novel structure is provided. One embodiment of the present invention is a semiconductor device including a memory module. The memory module includes a first memory cell, a first wiring, and a second wiring and a third wiring that include a metal oxide. The first memory cell includes a read transistor and a rewrite transistor. The first wiring includes a region functioning as a back gate of the read transistor and a region where the second wiring functions as a conductor. The second wiring includes a region functioning as a channel formation region of the read transistor, a region functioning as a back gate of the rewrite transistor, and a region where the third wiring functions as a conductor. The third wiring includes a region functioning as a channel formation region of the rewrite transistor and a region functioning as a conductor.

公开(公告)号：US20220271669A1

公开(公告)日：2022-08-25

申请号：US17612387

申请日：2020-05-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuto YAKUBO ,  Hitoshi KUNITAKE ,  Takayuki IKEDA

IPC: H02M3/158 ,  H02M1/34 ,  H01L29/786

Abstract: A semiconductor device in which an increase in circuit area is inhibited is provided. The semiconductor device includes a first circuit layer and a second circuit layer over the first circuit layer; the first circuit layer includes a first transistor; the second circuit layer includes a second transistor; a gate of the second transistor is electrically connected to one of a source and a drain of the first transistor; a source and a drain of the second transistor are electrically connected to the other of the source and the drain of the first transistor; and a semiconductor layer of the second transistor contains a metal oxide.

公开(公告)号：US20220246615A1

公开(公告)日：2022-08-04

申请号：US17612873

申请日：2020-05-19

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kazuaki OHSHIMA ,  Hitoshi KUNITAKE ,  Takahiro FUKUTOME

IPC: H01L27/108 ,  H01L27/12 ,  H01L29/786

Abstract: A semiconductor device in which temperature dependence is reduced is provided. A switched capacitor is formed using a second transistor, a third transistor, and a second capacitor. Semiconductor layers of the second transistor and the third transistor that include an oxide can reduce temperature dependence. An AC signal supplied to the gates of the second transistor and the third transistor is converted into a DC voltage through the switched capacitor. Note that the level of the DC voltage is adjusted by the levels of the voltages supplied to the back gates of the second transistor and the third transistor.

公开(公告)号：US20220238560A1

公开(公告)日：2022-07-28

申请号：US17615780

申请日：2020-05-22

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hitoshi KUNITAKE ,  Kazuki TSUDA

IPC: H01L27/12 ,  H01L29/786

Abstract: Malfunctions of a circuit is prevented and the reliability of a semiconductor device using the circuit is improved. The semiconductor device includes a first transistor, a second transistor, a load, and a wiring having a function of supplying a power supply potential to the load. A semiconductor layer of the first transistor includes an oxide semiconductor. A semiconductor layer of the second transistor includes an oxide semiconductor. A source and a drain of the first transistor are electrically connected to the wiring. A first gate of the first transistor is supplied with a reference potential. A source and a drain of the second transistor are supplied with the reference potential. A first gate of the second transistor is electrically connected to the wiring. The semiconductor layer of the first transistor includes a region overlapping with the wiring. The semiconductor layer of the second transistor includes a region overlapping with the wiring.

公开(公告)号：US20220238525A1

公开(公告)日：2022-07-28

申请号：US17616441

申请日：2020-05-25

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hitoshi KUNITAKE ,  Takayuki IKEDA ,  Takahiro FUKUTOME

IPC: H01L27/108 ,  H01L27/12 ,  H01L29/786

Abstract: A small-size semiconductor device is provided. The semiconductor device includes a first layer, a second layer, and a third layer formed over a substrate. A first transistor included in the first layer includes a first semiconductor layer containing Si. A second transistor included in the second layer includes a second semiconductor layer containing Ga. A third transistor included in the third layer includes a third semiconductor layer containing at least one of In and Zn. The first semiconductor layer of the first transistor is formed using the substrate. The second semiconductor layer of the second transistor is formed using a crystal obtained by crystal growth over the substrate. The third semiconductor layer of the third transistor is formed above the first semiconductor layer and the second semiconductor layer.

公开(公告)号：US20220231644A1

公开(公告)日：2022-07-21

申请号：US17614690

申请日：2020-05-22

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Minato ITO ,  Hitoshi KUNITAKE ,  Takayuki IKEDA

IPC: H03F3/45 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786

Abstract: A semiconductor device that functions as a relay station and is reduced in size is provided. The semiconductor device includes an operational amplifier, a first transistor and a first capacitor that are electrically connected to a first input side of the operational amplifier, and a first resistor and a second resistor that are electrically connected to a second input side. The second resistor is electrically connected to an output side of the operational amplifier, a gate of the first transistor is electrically connected to a first power supply, the first resistor is electrically connected to a second power supply, and at least a transistor included in the operational amplifier has a region overlapping with the first transistor.

公开(公告)号：US20220199653A1

公开(公告)日：2022-06-23

申请号：US17611689

申请日：2020-05-18

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yuto YAKUBO ,  Hitoshi KUNITAKE ,  Takayuki IKEDA

IPC: H01L27/12 ,  H03B5/12

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes an oscillation circuit including a first coil, a second coil, a first capacitor, a second capacitor, a first transistor, and a second transistor and a frequency correction circuit including a third capacitor, a fourth capacitor, a third transistor, a fourth transistor, and a switching circuit. The switching circuit has a function of controlling a conduction state or a non-conduction state of the third transistor and the fourth transistor. The frequency correction circuit is provided above the oscillation circuit and has a function of adjusting an oscillation frequency of the oscillation circuit. The first transistor and the second transistor each include a semiconductor layer containing silicon in a channel formation region. The third transistor and the fourth transistor each include a semiconductor layer containing an oxide semiconductor in a channel formation region.

公开(公告)号：US20220085019A1

公开(公告)日：2022-03-17

申请号：US17419745

申请日：2020-02-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hitoshi KUNITAKE ,  Tatsuya ONUKI ,  Tomoaki ATSUMI ,  Kiyoshi KATO

IPC: H01L27/108 ,  H01L21/8239 ,  H01L29/786 ,  G11C29/52

Abstract: A memory device having an error detection function and being capable of storing a large amount of data per unit area is provided. A driver circuit of the memory device is formed using a transistor formed on a semiconductor substrate, and a memory cell of the memory device is formed using a thin film transistor. A plurality of layers each of which includes a memory cell using the thin film transistor can be stacked over the semiconductor substrate, so that the amount of data that can be stored per unit area can be increased. Part of a peripheral circuit including the memory device can be formed using a thin film transistor, and thus, an error detection circuit is formed using the thin film transistor and stacked over the semiconductor substrate.

公开(公告)号：US20210036025A1

公开(公告)日：2021-02-04

申请号：US16964115

申请日：2019-01-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hitoshi KUNITAKE ,  Shuhei NAGATSUKA

IPC: H01L27/12 ,  H01L27/13

Abstract: A semiconductor device in which an electrification phenomenon that leads to characteristic fluctuations, element deterioration, or dielectric breakdown is inhibited is provided. A first transistor, a second transistor, a third transistor, and a fourth transistor are included over a substrate; the fourth transistor includes a first conductor, a second conductor, a third conductor, and an oxide semiconductor; the first conductor is electrically connected to the semiconductor substrate through the first transistor; the second conductor is electrically connected to the semiconductor substrate through the first transistor; the third conductor is electrically connected to the semiconductor substrate through the first transistor; and the fourth conductor is electrically connected to the semiconductor substrate through the first transistor.