公开(公告)号：US06281719B1

公开(公告)日：2001-08-28

申请号：US09431346

申请日：1999-10-29

申请人： Tien-Shin Ho ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  I-Long Lee ,  Ray Lin Wan

发明人： Tien-Shin Ho ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  I-Long Lee ,  Ray Lin Wan

IPC分类号： H03B100

CPC分类号： H03K19/01728 ,  H03K19/00315

摘要： An output driver for an integrated circuit performs a precharge function before internal data is available, minimizing the access time for such data. Also, the pull up and pull down circuitry used in the precharge function is separate from the output driver, and independent of the level of the data signal to be driven. A sense circuit senses an initial state of the output pad, before the output signal is supplied to the output pad, which indicates whether a voltage level on the output pad is above a threshold or below the threshold. A precharge circuit includes a pull up circuit and a pull down circuit. The pull up circuit is responsive to the initial state indicating that the voltage level on the output is below the threshold, and the pull down circuit is responsive to the initial state indicating that the voltage level on the output is above the threshold. A detector is coupled to the output, and produces a control signal indicating when output is near the threshold. Logic is responsive to the control signal from the detector to turn off the precharge circuit when the threshold is reached.

摘要翻译： 用于集成电路的输出驱动器在内部数据可用之前执行预充电功能，从而最小化这种数据的访问时间。 此外，预充电功能中使用的上拉和下拉电路与输出驱动器分离，并且与要驱动的数据信号的电平无关。 在输出信号被提供给输出焊盘之前，感测电路感测输出焊盘的初始状态，其指示输出焊盘上的电压电平是否高于阈值或低于阈值。 预充电电路包括上拉电路和下拉电路。 上拉电路响应于初始状态，指示输出上的电压电平低于阈值，并且下拉电路响应于初始状态，指示输出上的电压电平高于阈值。 检测器耦合到输出端，产生一个控制信号，指示何时输出接近阈值。 当达到阈值时，逻辑响应来自检测器的控制信号以关闭预充电电路。

公开(公告)号：US6031757A

公开(公告)日：2000-02-29

申请号：US825879

申请日：1997-04-02

申请人： Weitong Chuang ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Yin-Shang Liu ,  Yao-Wu Cheng

发明人： Weitong Chuang ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Yin-Shang Liu ,  Yao-Wu Cheng

IPC分类号： G11C16/22 ,  G11C16/04

CPC分类号： G11C16/22

摘要： A user-programmable write protection scheme provides flexibility and superior write protect features for an integrated circuit memory which comprises an array of non-volatile erasable and programmable memory cells, including a plurality of sectors. Command logic detects command sequences indicating operations for the array, including a program operation, a sector erase operation, a read operation, a sector lock operation, and a sector unlock operation. The sector protect logic includes sector lock memory, including non-volatile memory cells that store sector lock signals for at least one sector in the array. Among other functions, the sector protect logic: 1) inhibits sector erase and program operations to a particular sector in response to a set sector lock signal corresponding to the particular sector, and to a first state of control signals in the set of control signals; 2) enables sector erase and program operations in response to a reset sector lock signal corresponding to the particular sector, and to the first state of control signals in the set of control signals; 3) inhibits sector erase and program operations to the particular sector independent of the sector lock signal in response to a second state of control signals in the set of control signals; and 4) enables sector erase and program operations independent of the sector lock signal in response to a third state of control signals in the set of control signals.

摘要翻译： PCT No.PCT / US96 / 18674 Sec。 371日期1997年4月2日 102（e）日期1997年4月2日PCT提交1996年11月22日PCT公布。 第WO98 / 22950号公报 日期1998年5月28日用户可编程写保护方案为集成电路存储器提供灵活性和出色的写保护功能，其包括包括多个扇区的非易失性可擦除和可编程存储器单元的阵列。 命令逻辑检测指示阵列的操作的命令序列，包括程序操作，扇区擦除操作，读取操作，扇区锁定操作和扇区解锁操作。 扇区保护逻辑包括扇区锁定存储器，包括存储阵列中的至少一个扇区的扇区锁定信号的非易失性存储器单元。 在其他功能中，扇区保护逻辑：1）响应于对应于特定扇区的设置扇区锁定信号，以及控制信号组中的控制信号的第一状态，禁止对特定扇区的扇区擦除和编程操作; 2）响应于对应于特定扇区的复位扇区锁定信号和控制信号组中的控制信号的第一状态使能扇区擦除和编程操作; 3）响应于该组控制信号中的控制信号的第二状态，禁止与扇区锁定信号无关的扇区擦除和编程操作到特定扇区; 和4）响应于该组控制信号中的控制信号的第三状态，使扇区擦除和编程操作独立于扇区锁定信号。

公开(公告)号：US20130094319A1

公开(公告)日：2013-04-18

申请号：US13708150

申请日：2012-12-07

申请人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Hsieh Ming Chih

发明人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Hsieh Ming Chih

IPC分类号： G11C8/10

CPC分类号： G11C8/10 ,  G11C8/12

摘要： A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set of address bits. The high order set of address bits and the low order set of address bits constitute a complete access address of the memory integrated circuit. The first command and the second command have different in command codes.

摘要翻译： 存储器集成电路具有访问存储器集成电路的存储单元的控制电路。 控制电路响应于包括第一命令和第二命令的命令。 第一个命令指定高位地址位集合。 第二个命令指定低位地址位集合。 地址位的高位集合和地址位的低位集合构成存储器集成电路的完整访问地址。 第一个命令和第二个命令在命令代码中有所不同。

公开(公告)号：US20120327722A1

公开(公告)日：2012-12-27

申请号：US13523060

申请日：2012-06-14

申请人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Chia-He Liu

发明人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Chia-He Liu

IPC分类号： G11C7/10

CPC分类号： G11C7/1045 ,  G11C7/1072 ,  G11C7/22

摘要： An integrated circuit includes a serial peripheral interface memory device. In an embodiment, the memory device includes a clock signal, a plurality of pins, and a configuration register. In an embodiment, the configuration register includes a wait cycle count. The method includes transmitting a read address to the memory device using a first input/output pin and a second input/output pin concurrently. In an embodiment, the read address includes at least a first address bit and a second address bit, the first address bit being transmitted using the first input/output pin, and the second address bit being transmitted using the second input/output pin. The method includes accessing the memory device for data associated with the address and waiting a predetermined number clock cycles associated with the wait cycle count. The method includes transferring the data from the memory device using the first input/output pin and the second input/output pin concurrently.

摘要翻译： 集成电路包括串行外设接口存储器件。 在一个实施例中，存储器件包括时钟信号，多个引脚和配置寄存器。 在一个实施例中，配置寄存器包括等待周期计数。 该方法包括使用第一输入/输出引脚和第二输入/输出引脚同时向存储器件发送读取地址。 在一个实施例中，读地址至少包括第一地址位和第二地址位，第一地址位使用第一输入/输出引脚发送，第二地址位使用第二输入/输出引脚发送。 该方法包括访问与该地址相关联的数据的存储设备，并等待与等待周期计数相关联的预定数量的时钟周期。 该方法包括使用第一输入/输出引脚和第二输入/输出引脚同时从存储器件传送数据。

公开(公告)号：US20120268987A1

公开(公告)日：2012-10-25

申请号：US13539831

申请日：2012-07-02

申请人： Chun-Hsiung Hung ,  Jeng-Kuan Lin ,  Kuen-Long Chang

发明人： Chun-Hsiung Hung ,  Jeng-Kuan Lin ,  Kuen-Long Chang

IPC分类号： G11C16/06

CPC分类号： G11C16/3418 ,  G11C16/28

摘要： A method of detecting a disturb condition of a memory cell includes application of multiple sets of conditions to the memory cell and determining whether the memory cell behaves as a programmed memory cell in response to the sets of conditions. A disturbed memory cell can be detected if the memory cell responds as a programmed memory cell in response to one of the sets of conditions, but responds as an erased memory cell in response to another of the sets of conditions.

摘要翻译： 一种检测存储器单元的干扰状况的方法包括将多组条件应用于存储单元，并根据条件集确定存储单元是否作为编程存储器单元。 如果存储器单元响应于一组条件而作为编程存储器单元进行响应，则可以检测到干扰的存储器单元，而是响应于另一组条件而被响应为擦除存储器单元。

公开(公告)号：US08238162B2

公开(公告)日：2012-08-07

申请号：US12868228

申请日：2010-08-25

申请人： Chun-Hsiung Hung ,  Jeng-Kuan Lin ,  Kuen-Long Chang

发明人： Chun-Hsiung Hung ,  Jeng-Kuan Lin ,  Kuen-Long Chang

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06 ,  G11C5/06

CPC分类号： G11C16/3418 ,  G11C16/28

摘要： A method of detecting a disturb condition of a memory cell includes application of multiple sets of conditions to the memory cell and determining whether the memory cell behaves as a programmed memory cell in response to the sets of conditions. A disturbed memory cell can be detected if the memory cell responds as a programmed memory cell in response to one of the sets of conditions, but responds as an erased memory cell in response to another of the sets of conditions.

摘要翻译： 一种检测存储器单元的干扰状况的方法包括将多组条件应用于存储单元，并根据条件集确定存储单元是否作为编程存储器单元。 如果存储器单元响应于一组条件而作为编程存储器单元进行响应，则可以检测到干扰的存储器单元，而是响应于另一组条件而被响应为擦除存储器单元。

公开(公告)号：US20110238939A1

公开(公告)日：2011-09-29

申请号：US13155404

申请日：2011-06-08

申请人： Yu-Lan Kuo ,  Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Yu-Lan Kuo ,  Chun-Yi Lee ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G06F12/14

CPC分类号： G11C8/20 ,  G06F21/79 ,  G11C16/22

摘要： A memory device comprises a memory array, a status register, a status-register write-protect bit and a security register. The memory array contains a number of memory blocks. The status register includes at least one protection bit indicative of a protection status of at least one corresponding block of the memory blocks. The status-register write-protect bit is coupled with the status register for preventing a state change of the at least one protection bit. The security register includes at least one register-protection bit for preventing the state change in one of the at least one protection bit of the status register and the status-register write-protect bit.

摘要翻译： 存储器件包括存储器阵列，状态寄存器，状态寄存器写保护位和安全寄存器。 存储器阵列包含许多存储器块。 状态寄存器包括至少一个指示存储块的至少一个相应块的保护状态的保护位。 状态寄存器写保护位与状态寄存器耦合以防止至少一个保护位的状态改变。 安全寄存器包括至少一个用于防止状态寄存器的至少一个保护位和状态寄存器写保护位之一的状态改变的寄存器保护位。

公开(公告)号：US20110128809A1

公开(公告)日：2011-06-02

申请号：US12769456

申请日：2010-04-28

申请人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Hsieh-Ming Chih

发明人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Hsieh-Ming Chih

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C8/12

摘要： A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set of address bits. The high order set of address bits and the low order set of address bits constitute a complete access address of the memory integrated circuit. The first command and the second command have different in command codes.

摘要翻译： 存储器集成电路具有访问存储器集成电路的存储单元的控制电路。 控制电路响应于包括第一命令和第二命令的命令。 第一个命令指定高位地址位集合。 第二个命令指定低位地址位集合。 地址位的高位集合和地址位的低位集合构成存储器集成电路的完整访问地址。 第一个命令和第二个命令在命令代码中有所不同。

公开(公告)号：US20110128791A1

公开(公告)日：2011-06-02

申请号：US12834686

申请日：2010-07-12

申请人： Yi-Fan Chang ,  Cheng Ming Yih ,  Su-chueh Lo ,  Jian Shing Liu ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Yi-Fan Chang ,  Cheng Ming Yih ,  Su-chueh Lo ,  Jian Shing Liu ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C16/06 ,  G11C16/16

CPC分类号： G11C16/14 ,  G11C16/344 ,  G11C16/3477

摘要： Various discussed approaches include an improved grouping of edge word lines and center word lines of an erase group during erase verify and erase sub-operations of an erase operation. In another approach, changed voltage levels of edge word lines to address the over-erase issue of the erase group, and also improve erase time performance. Another approach uses dummy word lines.

摘要翻译： 各种讨论的方法包括在擦除验证和擦除擦除操作的子操作期间改进擦除组的边缘字线和中心字线的分组。 在另一种方法中，改变边缘字线的电压电平以解决擦除组的过擦除问题，并且还提高擦除时间性能。 另一种方法使用虚拟字线。

公开(公告)号：US20110085380A1

公开(公告)日：2011-04-14

申请号：US12970222

申请日：2010-12-16

申请人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

发明人： Wen-Chiao Ho ,  Chin-Hung Chang ,  Kuen-Long Chang ,  Chun-Hsiung Hung

IPC分类号： G11C16/10 ,  G11C16/04 ,  G11C16/34

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5642

摘要： A method of programming a memory, wherein the memory includes many memory regions having multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The protecting unit, coupled to the first and second bit lines, and the data buffer, prevents a programming error from occurring. In an embodiment of the programming method, corresponding data are inputted to the data buffers respectively. The data corresponding to an nth phase are programmed into the targeted multi-level cells. Data corresponding to an (n+1)th phase is modified to make the data corresponding to the (n+1)th phase be the same as the data corresponding to the nth phase if the targeted multi-level cells pass a programming verification process according to an nth programming verification voltage. The above steps are repeated until n is equal to a maximum, n being a positive integer.

摘要翻译： 一种对存储器进行编程的方法，其中所述存储器包括具有多个多电平单元的许多存储区域。 每个存储器区域包括第一位线，第二位线，数据缓冲器和保护单元。 耦合到第一和第二位线的保护单元和数据缓冲器防止编程错误发生。 在编程方法的实施例中，对应的数据分别输入到数据缓冲器。 对应于第n阶段的数据被编程到目标多级单元中。 修改对应于第（n + 1）个相位的数据，以使对应于第（n + 1）相的数据与对应于第n相的数据相同，如果目标多电平单元通过编程验证处理 根据第n个编程验证电压。 重复上述步骤直到n等于最大值，n为正整数。