公开(公告)号：US20050081209A1

公开(公告)日：2005-04-14

申请号：US10967433

申请日：2004-10-18

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki

IPC分类号： G06F12/14 ,  G06F15/16 ,  G06F15/80 ,  G06F21/24 ,  H04L29/06 ,  G06F9/46

CPC分类号： G06F12/1466 ,  H04L69/12

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A processing system for processing computer tasks is also provided. A first processor is of a first processor type and a number of second processors are of a second processor type. One of the second processors manages process scheduling of computing tasks by providing tasks to at least one of the first and second processors.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 还提供了一种用于处理计算机任务的处理系统。 第一处理器是第一处理器类型，并且多个第二处理器是第二处理器类型。 第二处理器之一通过向第一和第二处理器中的至少一个提供任务来管理计算任务的进程调度。

公开(公告)号：US06549676B1

公开(公告)日：2003-04-15

申请号：US09412432

申请日：1999-10-05

申请人： Tadayoshi Nakayama ,  Hiroshi Kajiwara ,  Takeshi Yamazaki

发明人： Tadayoshi Nakayama ,  Hiroshi Kajiwara ,  Takeshi Yamazaki

IPC分类号： G06K936

CPC分类号： G06T9/004

摘要： The objective of the present invention is to perform fast variable-length coding that is applied for lossless compression and encoding. To achieve this objective, an encoding device comprises a unit for determining, from a plurality of states, states of peripheral pixels of an object pixel to be encoded, a unit for producing a predicted value of the object pixel based on the peripheral pixels, a memory used for storing a k parameter (k≦0) for each of the plurality of states, a unit for encoding a prediction difference between the value of the object pixel and a predicted value to variable-length code having a code length that is obtained by using the prediction difference and the k parameter that is stored in the memory and corresponds to the state determined by the state determination unit and a unit for, after variable-length encoding is performed for the object pixel, updating in advance the k parameter in order to perform variable-length encoding for another pixel that has the same state as the state determined by the state determination unit, and for writing the k parameter to the memory.

摘要翻译： 本发明的目的是执行用于无损压缩和编码的快速可变长度编码。 为了实现该目的，编码装置包括用于从多个状态确定要编码的对象像素的周边像素的状态的单元，用于基于周边像素产生对象像素的预测值的单元， 用于存储多个状态中的每一个的ak参数（k <= 0）的存储器，用于将对象像素的值与预测值之间的预测差编码为具有获得的代码长度的可变长度代码的单元 通过使用存储在存储器中的预测差和k参数，并且对应于由状态确定单元确定的状态，并且在针对对象像素执行可变长度编码之后的单元，预先更新k参数 为与由状态判定单元确定的状态具有相同状态的另一像素执行可变长度编码，并将k参数写入存储器。

公开(公告)号：US06546129B1

公开(公告)日：2003-04-08

申请号：US08963984

申请日：1997-11-04

申请人： Takatoshi Ohta ,  Ryuichi Arai ,  Munehiko Ohta ,  Hiroaki Sugiura ,  Toshihiro Nakazawa ,  Takeshi Yamazaki

发明人： Takatoshi Ohta ,  Ryuichi Arai ,  Munehiko Ohta ,  Hiroaki Sugiura ,  Toshihiro Nakazawa ,  Takeshi Yamazaki

IPC分类号： G06K900

CPC分类号： H04N1/00867 ,  G07D7/12 ,  G07D7/20 ,  H04N1/0087 ,  H04N2201/3205 ,  H04N2201/327

摘要： In case of managing image data among plural image processing apparatuses, an object of the present invention is to suppress or restrain, as much as possible, that the image data is illegally or unfairly used. In order to achieve the object, e.g., it is provided an image processing apparatus which is connected to an external apparatus being an output destination of the image data, the image processing apparatus comprises an input means for inputting the image data representing an image, an addition means for adding additional information capable of specifying the external apparatus to the image data inputted by the input means, in a state that the additional information is difficult to be perceived by human eyes, and an output means for outputting the image data to which the additional information was added by the addition means, to the external apparatus.

摘要翻译： 在多个图像处理装置中管理图像数据的情况下，本发明的目的是尽可能地抑制或限制图像数据被非法或不公平地使用。 为了实现该目的，例如，提供了连接到作为图像数据的输出目的地的外部设备的图像处理装置，图像处理装置包括用于输入表示图像的图像数据的输入装置， 附加装置，用于在附加信息难以被人眼察觉的状态下，将能够指定外部装置的附加信息添加到由输入装置输入的图像数据;以及输出装置，用于输出图像数据， 通过添加装置将附加信息添加到外部设备。

公开(公告)号：US6054793A

公开(公告)日：2000-04-25

申请号：US159713

申请日：1998-09-24

申请人： Yutaka Kawai ,  Takeshi Yamazaki

发明人： Yutaka Kawai ,  Takeshi Yamazaki

IPC分类号： H01L41/08 ,  H01L41/083 ,  H03H20060101 ,  H03H3/04 ,  H03H9/00 ,  H03H9/02 ,  H03H9/10 ,  H03H9/15 ,  H03H9/17 ,  H03H9/205 ,  H03H9/58 ,  H04B1/26

CPC分类号： H03H9/178 ,  H03H3/04 ,  H03H9/1014

摘要： A base member of a piezoelectric resonator includes a laminated body having a plurality of piezoelectric layers which are alternately polarized in opposite directions along the longitudinal direction of the base member and inner electrodes provided between the piezoelectric layers. On a first side surface of the base member, each of two external electrodes is arranged so as to be connected to one of two groups of alternate inner electrodes. Cut portions for adjusting a frequency of the piezoelectric resonator to a higher frequency are respectively formed at edge portions of the base member at opposite ends in the longitudinal direction of a second side surface opposite from the first side surface of the base member.

摘要翻译： 压电谐振器的基座部件包括具有多个压电层的叠层体，所述多个压电层沿着基底部件的长度方向相反的方向交替极化，而内部电极设置在压电层之间。 在基体的第一侧表面上，两个外部电极中的每一个被布置成连接到两组交替的内部电极中的一组。 用于将压电谐振器的频率调节到较高频率的切割部分分别形成在与基底构件的第一侧表面相对的第二侧表面的纵向方向上的相对端处的基底构件的边缘部分处。

公开(公告)号：US5923855A

公开(公告)日：1999-07-13

申请号：US692346

申请日：1996-08-05

申请人： Takeshi Yamazaki

发明人： Takeshi Yamazaki

IPC分类号： G06F15/16 ,  G06F12/08 ,  G06F15/163

CPC分类号： G06F12/0815

摘要： In a multi-processor system including a plurality of processing units each having a cache memory, the processing units each include a synchronization counter for indicating a present synchronization state of the respective processing unit, and a cache state table for holding information regarding the respective entries of the cache memory. The cache state table includes a cache state and a cache synchronization count. The cache state holds the respective cache state used in a cache protocol. The cache synchronization count holds a value of the synchronization counter when an entry is loaded. A cache protocol in the multi-processor system is simplified to realize a high-speed processing.

摘要翻译： 在包括多个具有高速缓存存储器的处理单元的多处理器系统中，处理单元各自包括用于指示各个处理单元的当前同步状态的同步计数器，以及用于保存关于各个条目的信息的高速缓存状态表 的缓存内存。 高速缓存状态表包括高速缓存状态和高速缓存同步计数。 高速缓存状态保持缓存协议中使用的各自的高速缓存状态。 当加载条目时，高速缓存同步计数保持同步计数器的值。 多处理器系统中的缓存协议被简化以实现高速处理。

公开(公告)号：US5649141A

公开(公告)日：1997-07-15

申请号：US497447

申请日：1995-06-30

申请人： Takeshi Yamazaki

发明人： Takeshi Yamazaki

IPC分类号： G06F15/16 ,  G06F12/02 ,  G06F12/10 ,  G06F15/177

CPC分类号： G06F12/1072 ,  G06F12/0284

摘要： An address translation technique used in a multiprocessor system is disclosed. In a multiprocessor system for connecting a plurality of clusters with each other via a network, each of these clusters is arranged by comprising a plurality of processors; a cluster translator for translating a cluster number; a cluster translation table for storing therein a correspondence relationship between a logical cluster number and a physical cluster number; an address translator for translating an address; and an address translation table for storing therein a correspondence relationship between a logical address and a physical address. The address translation table stores only the data corresponding to a memory employed in the cluster. Accordingly, a total storage capacity of the address translation tables is reduced, and an updating operation of the address translation tables is simplified. Furthermore, the address translation table is exclusively identified based on a local job number and the cluster number, so that operation to update the address translation table is simplified.

摘要翻译： 公开了一种在多处理器系统中使用的地址转换技术。 在用于经由网络将多个集群彼此连接的多处理器系统中，通过包括多个处理器来布置这些集群中的每一个; 用于翻译簇号的群集翻译器; 集群转换表，用于在其中存储逻辑簇号和物理簇号之间的对应关系; 用于翻译地址的地址转换器; 以及用于在其中存储逻辑地址和物理地址之间的对应关系的地址转换表。 地址转换表仅存储与集群中使用的存储器相对应的数据。 因此，减少了地址转换表的总存储容量，并简化了地址转换表的更新操作。 此外，地址转换表是基于本地作业号和簇号唯一地标识的，因此简化了更新地址转换表的操作。

公开(公告)号：US5648946A

公开(公告)日：1997-07-15

申请号：US341087

申请日：1994-11-17

申请人： Takeshi Yamazaki

发明人： Takeshi Yamazaki

IPC分类号： G11B7/09 ,  G11B7/12 ,  G11B7/13 ,  G11B7/135

CPC分类号： G11B7/1353 ,  G11B7/0943 ,  G11B7/123 ,  G11B7/131 ,  G11B7/0903 ,  G11B7/0909 ,  G11B7/0912

摘要： An optical pick-up apparatus for recording and/or reading information on and/or from an optical record medium including a semiconductor substrate, a semiconductor laser arranged on the semiconductor substrate, plurality of photodetectors formed in the surface of the semiconductor substrate, a diffraction gratings dividing a laser beam into main beam and two sub-beams, an objective lens projecting the main and sub-beams onto the record medium and directing these beams reflected by the record medium toward a hologram which diffracts each of the main and sub-beams into .+-.1-order beams which are received by the photodetectors. The apparatus is constructed to satisfy the following conditions:NA.multidot.d d/.beta..sup.2 >0.01 mmwherein L mm is a distance between a spot of the main beam and a spot of a sub-beam on the record medium, NA is a numerical aperture of the objective lens on a side of the semiconductor laser, .beta. is a magnification of the objective lens viewed from the record medium to the semiconductor laser and d is a deviation of focal points of +1-order beams and -1-order beams viewed along an optical axis.

摘要翻译： 一种光学拾取装置，用于在包括半导体衬底的光学记录介质和布置在半导体衬底上的半导体激光器，在半导体衬底的表面中形成的多个光电检测器，和/ 将激光束分成主光束和两个子光束的光栅，物镜将主光束和子光束投影到记录介质上，并将这些由记录介质反射的光束引向全息图，衍射各主光束和副光束 由光电检测器接收的+/- 1级光束。 该装置被构造成满足以下条件：NAxd <|Lxβ| 0.04mm> d /β2> 0.01mm其中L mm是主波束的点与记录上的子光束点之间的距离 介质NA是半导体激光器一侧的物镜的数值孔径，β是从记录介质到半导体激光器的物镜的倍率，d是+ 1级光束的焦点偏差 和沿光轴观察的-1级光束。

公开(公告)号：US5608695A

公开(公告)日：1997-03-04

申请号：US337190

申请日：1994-11-07

申请人： Takeshi Yamazaki

发明人： Takeshi Yamazaki

IPC分类号： G11B7/09 ,  G11B7/12 ,  G11B7/135 ,  H01S5/022 ,  H01S5/183

CPC分类号： G11B7/1353 ,  G11B7/0901 ,  G11B7/123 ,  G11B7/0912 ,  H01S5/02296 ,  H01S5/0264 ,  H01S5/183

摘要： An optical pick-up apparatus for reading and/or writing information from and/or on an optical record medium including a semiconductor laser, an objective lens projecting a laser beam onto the optical record medium, a hologram optical element having a first hologram for diffracting the laser beam onto a first pair of photodetectors to derive a focusing error and a second hologram for diffracting the laser beam onto a second pair of photodetectors to derive a tracking error. Each of the photodetectors of the second pair has light receiving regions which are divided along a division line substantially parallel with a diffracting direction of the second hologram which introduces astigmatism into the diffracted beams. A large tracking error signal can be detected stably on the basis of a distribution of an amount of light in a far field by the push-pull method.

摘要翻译： 一种光学拾取装置，用于从包括半导体激光器的光学记录介质和/或将光学记录介质上的激光束投影的物镜读取和/或写入信息，具有用于衍射的第一全息图的全息光学元件 激光束到第一对光电检测器上以导出聚焦误差和第二全息图，用于将激光束衍射到第二对光电检测器上以导出跟踪误差。 第二对的每个光电检测器具有沿着与第二全息图的衍射方向大致平行的分割线分割的光接收区域，该散射方向将散光引入衍射光束。 基于通过推挽法在远场中的光量的分布，可以稳定地检测大的跟踪误差信号。

公开(公告)号：US5607209A

公开(公告)日：1997-03-04

申请号：US465056

申请日：1995-06-05

申请人： Tomohiro Narita ,  Hiroki Tsuge ,  Susumu Nishikawa ,  Kazumi Ishida ,  Takeshi Yamazaki

发明人： Tomohiro Narita ,  Hiroki Tsuge ,  Susumu Nishikawa ,  Kazumi Ishida ,  Takeshi Yamazaki

IPC分类号： B60T8/1761 ,  B60T8/32 ,  B60T13/66 ,  B60T13/52 ,  B60T13/68

CPC分类号： B60T8/17616 ,  B60T13/662 ,  B60T8/3275 ,  B60T2201/03 ,  B60T2240/08

摘要： When a brake pedal is operated by the vehicle driver, and detection signals from hydraulic pressure sensors and a brake switch, for detecting pressure of the brake pedal, are supplied to an ECU, the ECU performs a determination according to the detection signals as to whether or not the hydraulic pressure PM is a maximum pressure gradient d(PM)/dtmax. When the determination result of the braking condition is an emergency braking condition, an intake valve is opened. Thereafter, atmosphere is forcibly supplied to atmospheric chambers of a booster, to assist the braking force.

摘要翻译： 当车辆驾驶员操作制动踏板时，将用于检测制动踏板的压力的液压传感器和制动开关的检测信号提供给ECU，ECU根据检测信号进行关于是否 或者液压PM不是最大压力梯度d（PM）/ dtmax。 当制动条件的确定结果是紧急制动条件时，打开进气门。 此后，强制地将气氛供给到增压器的大气室，以辅助制动力。

公开(公告)号：US5523248A

公开(公告)日：1996-06-04

申请号：US447008

申请日：1995-05-22

申请人： Takeshi Yamazaki

发明人： Takeshi Yamazaki

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L21/265

CPC分类号： H01L21/823493 ,  H01L27/088

摘要： A semiconductor device in which low voltage elements and high voltage elements are formed on the same substrate. To simplify the manufacturing process of semiconductor devices and to improve the punch through voltage resistance between elements, when high voltage elements and low voltage elements are formed on the same semiconductor substrate, during the process for injecting p-type impurity into semiconductor substrate in the low voltage sections, at first a mask pattern having openings above the low voltage sections and openings above the element separating areas of the high voltage sections is formed, then p-type impurity is injected into the semiconductor substrate from above the mask pattern, followed by heat-treatment of the semiconductor substrate to diffuse p-type impurity into the semiconductor substrate. Thereby, channel stop diffusion layers comprising p-type impurity layer are formed under the element separating areas formed in the high voltage sections.

摘要翻译： 在同一衬底上形成低电压元件和高电压元件的半导体器件。 为了简化半导体器件的制造过程，并且通过在同一半导体衬底上形成高电压元件和低电压元件，提高元件之间的穿通电压电阻，在将p型杂质注入到半导体衬底中的过程中 首先，形成具有在低压部分之上的开口的掩模图案，并且形成在高压部分的元件分离区域上方的开口，然后将p型杂质从掩模图案上方注入到半导体衬底中，随后加热 处理半导体衬底以将p型杂质扩散到半导体衬底中。 由此，在形成于高压部的元件分离区域的下方形成包含p型杂质层的沟道阻挡扩散层。