公开(公告)号：US08867281B2

公开(公告)日：2014-10-21

申请号：US13958410

申请日：2013-08-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/00 ,  H02M3/156 ,  G11C16/06 ,  G11C5/14

CPC classification number: G11C16/06 ,  G11C5/145 ,  G11C16/12 ,  G11C16/30 ,  H02M3/07 ,  H02M3/073

Abstract: A hybrid charge pump and control circuit for use in a memory device is disclosed.

Abstract translation: 公开了一种用于存储器件的混合电荷泵和控制电路。

公开(公告)号：US11935594B2

公开(公告)日：2024-03-19

申请号：US17672617

申请日：2022-02-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Anh Ly

IPC: G11C16/08 ,  G06N3/065 ,  G11C11/54

CPC classification number: G11C16/08 ,  G06N3/065 ,  G11C11/54

Abstract: Various embodiments of tandem row decoders are disclosed. Each embodiment of a tandem row decoder comprises a word line decoder and a control gate decoder. The tandem row decoder exhibits reduced leakage current on the word line and the control gate line when the tandem row decoder is not enabled.

公开(公告)号：US11875852B2

公开(公告)日：2024-01-16

申请号：US17140924

申请日：2021-01-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Anh Ly ,  Nhan Do ,  Mark Reiten

IPC: G11C7/12 ,  G11C16/08 ,  G11C11/54 ,  G11C16/24

CPC classification number: G11C16/08 ,  G11C11/54 ,  G11C16/24 ,  G11C2216/04

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. Certain embodiments comprise an adaptive bias decoder for providing additional bias to array input lines to compensate for instances where ground floats above 0V. This is useful, for example, to minimize the voltage drop for a read, program, or erase operation while maintaining accuracy in the operation.

公开(公告)号：US11798619B2

公开(公告)日：2023-10-24

申请号：US17857113

申请日：2022-07-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly ,  Steven Lemke ,  Vipin Tiwari ,  Nhan Do

IPC: G11C11/54 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  G11C16/34 ,  G11C16/10 ,  G06N3/065

CPC classification number: G11C11/54 ,  G06N3/065 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3418 ,  G11C2216/04

Abstract: Numerous examples for performing tuning of a page or a word of non-volatile memory cells in an analog neural memory are disclosed. In one example, a method comprises programming a word or page of non-volatile memory cells in an analog neural memory system; and identifying any fast bits in the word or page of non-volatile memory cells.

公开(公告)号：US11783904B2

公开(公告)日：2023-10-10

申请号：US17839294

申请日：2022-06-13

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly ,  Steven Lemke ,  Nha Nguyen ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/34 ,  G11C16/10 ,  G06N3/063 ,  G06F3/06 ,  G06N3/08 ,  G11C16/26 ,  G11C29/10

CPC classification number: G11C16/3459 ,  G06F3/0688 ,  G06N3/063 ,  G06N3/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3436 ,  G11C29/10

Abstract: In one example, a method is disclosed of compensating for leakage in an array of analog neural non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bitline, the method comprising measuring leakage for a column of analog neural non-volatile memory cells coupled to a bitline; storing the measured leakage value; and applying the measured leakage value during a read operation of the column of analog neural non-volatile memory cells to compensate for the leakage.

公开(公告)号：US20230119017A1

公开(公告)日：2023-04-20

申请号：US18081124

申请日：2022-12-14

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly

IPC: G06N3/065 ,  G11C16/10 ,  G11C16/04 ,  G06N3/08 ,  G06F12/0811 ,  G11C11/4063 ,  G11C11/54

Abstract: Examples of programming circuits and methods are provided. In one example, an adjustable programming circuit comprises a first adjustable voltage divider; a second adjustable voltage divider; a first operational amplifier, wherein an output terminal of the first operational amplifier provides a first programming voltage; and a second operational amplifier, wherein the first input terminal of the second operational amplifier is coupled to the output terminal of the second operational amplifier and the first input terminal of the second operational amplifier is coupled to the second output terminal of the first adjustable voltage divider.

公开(公告)号：US20230049032A1

公开(公告)日：2023-02-16

申请号：US17521772

申请日：2021-11-08

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu

IPC: G06N3/063 ,  G11C16/26

Abstract: Numerous embodiments of output circuitry for an analog neural memory in a deep learning artificial neural network are disclosed. In some embodiments, a common mode circuit is used with differential cells, W+ and W−, that together store a weight, W. The common mode circuit can utilize current sources, variable resistors, or transistors as part of the structure for introducing a common mode voltage bias.

公开(公告)号：US20220254414A1

公开(公告)日：2022-08-11

申请号：US17734807

申请日：2022-05-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Anh Ly ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/04 ,  G06N3/08 ,  H01L27/11521 ,  H01L29/788

Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. In one example, a method for programming a plurality of non-volatile memory cells in an array of non-volatile memory cells, comprises generating a high voltage, and programming a plurality of non-volatile memory cells in an array using the high voltage when a programming enable signal is asserted and providing a feedback loop to maintain the high voltage while programming the plurality of non-volatile memory cells.

公开(公告)号：US11355184B2

公开(公告)日：2022-06-07

申请号：US16986812

申请日：2020-08-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly ,  Vipin Tiwari

IPC: G11C11/54 ,  G11C16/04 ,  G06N3/063 ,  G11C16/26 ,  G11C16/28 ,  H03F3/00 ,  H03M1/16 ,  H03M1/38

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. In certain embodiments, each memory cell in the array has an approximately constant source impedance when that cell is being operated. In certain embodiments, power consumption is substantially constant from bit line to bit line within the array when cells are being read. In certain embodiments, weight mapping is performed adaptively for optimal performance in power and noise.

公开(公告)号：US11289164B2

公开(公告)日：2022-03-29

申请号：US17104385

申请日：2020-11-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Anh Ly

IPC: G11C16/08 ,  G06N3/06 ,  G06N3/063 ,  G11C11/54

Abstract: Various embodiments of tandem row decoders are disclosed. Each embodiment of a tandem row decoder comprises a word line decoder and a control gate decoder. The tandem row decoder exhibits reduced leakage current on the word line and the control gate line when the tandem row decoder is not enabled.