公开(公告)号：US06787908B2

公开(公告)日：2004-09-07

申请号：US09874606

申请日：2001-06-05

Applicant: Steven L Skala ,  Subhas Bothra ,  Emmanuel Demuizon

Inventor： Steven L Skala ,  Subhas Bothra ,  Emmanuel Demuizon

IPC: H01L2144

CPC classification number: H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/13099 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/29099

Abstract: Metal bond pads are formed over active circuitry in a semiconductor chip in a reliable and cost effective manner. According to an example embodiment of the present invention, a metal bond pad is formed over circuitry in the semiconductor chip. A metal layer is formed over the circuitry and the metal bond pad, and a diffusion barrier layer is formed between the metal layer and the metal bond pad. In this manner, additional metal can be formed on the pad site using only one additional mask step, and thicker metal at the pad site improves the reliability of the chip by providing for a metal cushion at the pad useful in subsequent wire bonding processes.

Abstract translation: 金属接合焊盘以可靠和成本有效的方式在半导体芯片中的有源电路上形成。 根据本发明的示例性实施例，在半导体芯片中的电路上形成金属焊盘。 在电路和金属接合焊盘上形成金属层，并且在金属层和金属焊盘之间形成扩散阻挡层。 以这种方式，可以仅使用一个额外的掩模步骤在焊盘位置上形成额外的金属，并且在焊盘位置处的较厚的金属通过在随后的引线接合工艺中提供用于垫的金属衬垫来提高芯片的可靠性。

公开(公告)号：US06756316B1

公开(公告)日：2004-06-29

申请号：US09304798

申请日：1999-05-04

Applicant: Subhas Bothra ,  Harlan Lee Sur, Jr.

Inventor： Subhas Bothra ,  Harlan Lee Sur, Jr.

IPC: H01L21302

CPC classification number: B81C1/00047 ,  B81B2201/0235 ,  B81B2201/0264 ,  B81B2207/07 ,  G01L9/0042

Abstract: Disclosed is a method for making a semiconductor pressure transducer structure in CMOS integrated circuits. The method includes patterning a first metallization layer that lies over an first oxide layer to produce a first patterned metallization layer that is not in electrical contact with a substrate. Forming a tungsten plug in a second oxide layer that overlies the first patterned metallization layer, such that the tungsten plug is in electrical contact with the first patterned metallization layer. Patterning a second metallization layer that overlies the first patterned metallization layer and the tungsten plug to produce a second patterned metallization layer. The patterning of the second metallization layer is configured to prevent the second patterned metallization layer from completely overlying the tungsten plug. The method further includes submerging the pressure transducer structure in a basic solution having a pH level that is greater than about 7. In this manner, the tungsten plug will come in direct contact with the basic solution that causes the tungsten plug to be removed while the pressure transducer structure is submerged in the basic solution.

Abstract translation: 公开了一种在CMOS集成电路中制造半导体压力传感器结构的方法。 该方法包括图案化位于第一氧化物层之上的第一金属化层以产生不与衬底电接触的第一图案化金属化层。 在覆盖在第一图案化金属化层上的第二氧化物层中形成钨插塞，使得钨插塞与第一图案化金属化层电接触。 将第二金属化层图案化成覆盖在第一图案化金属化层和钨插塞上以产生第二图案化金属化层。 第二金属化层的图案化被配置为防止第二图案化金属化层完全覆盖钨插塞。 该方法还包括将压力传感器结构浸入具有大于约7的pH水平的碱性溶液中。以这种方式，钨塞将与基本溶液直接接触，导致钨丝塞被去除，而 压力传感器结构浸没在基本解决方案中。

公开(公告)号：US06710425B2

公开(公告)日：2004-03-23

申请号：US09844293

申请日：2001-04-26

Applicant: Subhas Bothra

Inventor： Subhas Bothra

IPC: H01G406

CPC classification number: H01L28/40 ,  H01L21/76838 ,  H01L28/60 ,  Y10S257/906

Abstract: A high density MIM capacitor structure and method of manufacturing the same is disclosed for integrated circuits having multiple metal layer interconnections. The capacitor structure is formed between selected first and second metallic interconnections which are separated by an insulating intermetallic oxide layer. A first metal-dielectric-metal layer capacitor is created over and with a portion of the first metallic interconnection and a second metal-dielectric-metal layer capacitor is created under and with a portion of the second metallic interconnection. A first metal via through the insulating intermetallic oxide layer connects the first metal-dielectric-metal layer capacitor and the second metal-dielectric-metal layer capacitor to form a first terminal of the capacitor structure and a second metal via through the insulating intermetallic oxide layer connects the first metallic interconnection portion and the second metallic interconnection portion to form a second terminal of the capacitor structure. Damascene processes are used to manufacture the multiple metal layer interconnections.

Abstract translation: 公开了具有多个金属层互连的集成电路的高密度MIM电容器结构及其制造方法。 电容器结构形成在由绝缘金属间氧化物层分离的选择的第一和第二金属互连之间。 第一金属 - 电介质 - 金属层电容器在第一金属互连的一部分上并与第一金属互连的一部分产生，并且第二金属 - 电介质 - 金属层电容器被形成在第二金属互连的一部分之下。 通过绝缘金属间氧化物层的第一金属通孔连接第一金属 - 电介质 - 金属层电容器和第二金属 - 电介质 - 金属层电容器，以形成电容器结构的第一端子和通过绝缘金属间氧化物层的第二金属通孔 连接第一金属互连部分和第二金属互连部分以形成电容器结构的第二端子。 镶嵌工艺用于制造多层金属层互连。

公开(公告)号：US06573148B1

公开(公告)日：2003-06-03

申请号：US09614393

申请日：2000-07-12

Applicant: Subhas Bothra

Inventor： Subhas Bothra

IPC: H01L2120

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01F41/042 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor inductor and a method for making a semiconductor inductor are provided. An oxide layer disposed over a substrate is etched to form an interconnect metallization trench within the oxide layer. The oxide layer is also etched to form a first inductor trench within the oxide layer such that the first inductor trench is defined in an inductor geometry. The oxide layer is then etched to form at least one via in the interconnect metallization trench and a second inductor trench over the first inductor trench in the oxide layer. The second inductor trench also has the inductor geometry. After the oxide layer is etched, the at least one via, the second inductor trench, the interconnect metallization trench and the first inductor trench are filled with copper. The semiconductor inductor is configured to have a low resistance and a high quality factor.

Abstract translation: 提供半导体电感器和制造半导体电感器的方法。 蚀刻设置在衬底上的氧化物层以在氧化物层内形成互连金属化沟槽。 也蚀刻氧化物层以在氧化物层内形成第一电感器沟槽，使得第一电感器沟槽以电感器几何形状限定。 然后蚀刻氧化物层以在互连金属化沟槽中形成至少一个通孔，以及在氧化物层中的第一电感器沟槽上方的第二电感器沟槽。 第二电感沟槽也具有电感器几何形状。 在蚀刻氧化物层之后，铜填充至少一个通孔，第二电感器沟槽，互连金属化沟槽和第一电感器沟槽。 半导体电感器被配置为具有低电阻和高品质因数。

公开(公告)号：US06323113B1

公开(公告)日：2001-11-27

申请号：US09466988

申请日：1999-12-10

Applicant: Calvin T. Gabriel ,  Tammy D. Zheng ,  Subhas Bothra ,  Harlan L. Sur, Jr.

Inventor： Calvin T. Gabriel ,  Tammy D. Zheng ,  Subhas Bothra ,  Harlan L. Sur, Jr.

IPC: H01L2120

CPC classification number: H01L27/0207 ,  H01L21/76229

Abstract: The present invention provides methods for intelligently filling a gate layer with dummy fill patterns to produce a target pattern density. A gate layout defining gate areas on the gate layer is provided along with a diffusion layout defining active diffusion areas over a semiconductor substrate. For the gate layout, a pattern density is determined. Then, the areas not occupied by the gate areas and the diffusion areas are determined. Additionally, a range of pattern densities is provided in a set of predefined fill patterns with each predefined fill pattern having a plurality of dummy fill patterns and being associated with a pattern density within the provided range of pattern densities. Among the set of predefined fill patterns, a predefined fill pattern is selected for producing the target pattern density. Then, the gate layer is filled by placing the dummy fill patterns of the selected predefined fill pattern in the areas not occupied by the gate areas and the diffusion areas. In so doing, the target pattern density is provided in the gate layer when combined with the pattern density of the gate layout.

Abstract translation: 本发明提供了用虚拟填充图案智能地填充栅极层以产生目标图案密度的方法。 在栅极层上限定栅极区域的栅极布局与限定半导体衬底上的有源扩散区域的扩散布局一起提供。 对于门布局，确定图案密度。 然后，确定不被栅极区域和扩散区域占据的区域。 此外，在一组预定义的填充图案中提供了一系列图案密度，其中每个预定填充图案具有多个虚拟填充图案，并且与所提供的图案密度范围内的图案密度相关联。 在预定义的填充图案集合中，选择预定义的填充图案以产生目标图案密度。 然后，通过将所选择的预定填充图案的虚拟填充图案放置在未被栅极区域和扩散区域占据的区域中来填充栅极层。 这样做时，当与栅极布局的图案密度结合时，栅极层中提供目标图案密度。

公开(公告)号：US06313466B1

公开(公告)日：2001-11-06

申请号：US09310470

申请日：1999-05-12

Applicant: Christopher S. Olsen ,  Subhas Bothra

Inventor： Christopher S. Olsen ,  Subhas Bothra

IPC: H01L213205

CPC classification number: H01L21/3144

Abstract: In a method for determining the nitrogen concentration in a film of nitrided oxide material formed over a semiconductor wafer during fabrication of a semiconductor device an optical property of the film of nitrided oxide material is determined. The determined optical property is used to determine the nitrogen concentration in the film of nitrided oxide material. In one embodiment the optical property, e.g., extinction coefficient, k, is correlated to the nitrogen concentration measured by secondary ion mass spectroscopy. In a method of making a semiconductor device a film of nitrided oxide material is formed over a plurality of semiconductor wafers in a fab. The nitrogen concentration in the film of nitrided oxide material is monitored by periodically subjecting one of the wafers to an in-line test in the fab.

Abstract translation: 在半导体装置的制造中，确定在半导体晶片上形成的氮化氧化物材料的膜中的氮浓度的方法中，确定氮化氧化物材料的膜的光学特性。 确定的光学性质用于确定氮化氧化物材料的膜中的氮浓度。 在一个实施方案中，光学性质，例如消光系数k与通过二次离子质谱法测量的氮浓度相关。 在制造半导体器件的方法中，在晶圆厂中的多个半导体晶片上形成氮化氧化物材料的膜。 氮化氧化物材料膜中的氮浓度通过周期性地使一个晶片在晶圆厂中进行在线测试来监测。

公开(公告)号：US06189136B1

公开(公告)日：2001-02-13

申请号：US09119711

申请日：1998-07-20

Applicant: Subhas Bothra

Inventor： Subhas Bothra

IPC: G06F1750

CPC classification number: G03F7/70441 ,  G03F1/36

Abstract: A method for integrating correction features onto selected design features of an integrated circuit mask. The method includes identifying a minimum dimension in the integrated circuit mask. The minimum dimension is configured to define transistor gate electrode features or any critical feature geometry. The method then includes removing feature geometries that are dimensionally larger than the minimum dimension. After the removing operation, correction features are integrated with selected ends of the transistor electrode features that have the minimum dimension to produce corrected transistor gate electrode features. Then, the method includes the operation of adding the corrected transistor gate electrode features to the removed feature geometries that are dimensionally larger than the minimum dimension to produce a corrected integrated circuit mask.

Abstract translation: 一种用于将校正特征集成到集成电路掩模的选定设计特征上的方法。 该方法包括识别集成电路掩模中的最小尺寸。 最小尺寸被配置为定义晶体管栅电极特征或任何关键特征几何形状。 然后，该方法包括去除尺寸大于最小尺寸的特征几何。 在去除操作之后，校正特征与具有最小尺寸的晶体管电极特征的选定端集成以产生校正的晶体管栅电极特征。 然后，该方法包括将校正的晶体管栅电极特征与尺寸上大于最小尺寸的去除的特征几何相加以产生校正的集成电路掩模的操作。

公开(公告)号：US06176983B1

公开(公告)日：2001-01-23

申请号：US08923384

申请日：1997-09-03

Applicant: Subhas Bothra ,  Dipankar Pramanik ,  Samit Sengupta

Inventor： Subhas Bothra ,  Dipankar Pramanik ,  Samit Sengupta

IPC: C23C1434

CPC classification number: C23C14/046 ,  C23C14/345 ,  C23C14/35 ,  H01L21/76843 ,  H01L21/76877

Abstract: The present invention provides methods of forming a semiconductor workpiece. One method of forming a semiconductor device in accordance with the present invention includes: providing a semiconductor workpiece; forming a via within the semiconductor workpiece, the via including plural sidewalls joining a bottom surface at respective plural corners; first sputtering a process layer upon at least a portion of the bottom surface using ionized metal plasma physical vapor deposition; and following the sputtering of the process layer, second sputtering at least some of the process layer towards the corners within the via.

Abstract translation: 本发明提供了形成半导体工件的方法。 根据本发明的形成半导体器件的一种方法包括：提供半导体工件; 在所述半导体工件内形成通孔，所述通孔包括在相应的多个拐角处连接底表面的多个侧壁; 首先使用电离金属等离子体物理气相沉积在底表面的至少一部分上溅射处理层; 并且在溅射工艺层之后，将工艺层中的至少一些朝向通孔内的拐角第二溅射。

公开(公告)号：US6020647A

公开(公告)日：2000-02-01

申请号：US215902

申请日：1998-12-18

Applicant: Stephen L. Skala ,  Subhas Bothra ,  Dipu Pramanik ,  William Kuang-Hua Shu

Inventor： Stephen L. Skala ,  Subhas Bothra ,  Dipu Pramanik ,  William Kuang-Hua Shu

IPC: H01L23/485 ,  H01L29/41

CPC classification number: H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48599 ,  H01L2224/4943 ,  H01L2224/85201 ,  H01L24/45 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/14

Abstract: Disclosed is a semiconductor chip and method for making a semiconductor chip having strategically placed composite metallization. The semiconductor chip includes a topmost metallization layer that defines a plurality of patterned features including a plurality of input/output metallization pads for receiving an associated plurality of gold bonding wires. An inter-metal oxide layer that is defined under the topmost metallization layer. The semiconductor chip further includes an underlying metallization layer that is defined under the inter-metal oxide layer in order to electrically isolate the topmost metallization layer from the underlying metallization layer. The underlying metallization has a plurality of patterned features, and portions of the plurality of patterned features lie at least partially in locations that are underlying the plurality of input/output metallization pads. The portions of the plurality of patterned features are composite metallization regions that have a plurality of deformation preventing oxide patterns that are resistant to compression force induced plastic deformation that occurs when the plurality of gold bonding wires are applied.

Abstract translation: 公开了一种用于制造具有策略性地放置的复合金属化的半导体芯片的半导体芯片和方法。 半导体芯片包括最顶层金属化层，其限定多个图案化特征，包括用于接收相关联的多个金键合线的多个输入/输出金属化焊盘。 定义在最上层金属化层下面的金属间氧化物层。 该半导体芯片还包括下面的金属化层，其定义在金属间氧化物层之下，以将最上面的金属化层与下面的金属化层电隔离。 底层金属化具有多个图案化特征，并且多个图案化特征的部分至少部分地位于多个输入/输出金属化焊盘下方的位置。 多个图案化部分的部分是复合金属化区域，其具有多个防止变形的氧化物图案，其耐受在施加多个金焊丝时发生的压缩力引起的塑性变形。

公开(公告)号：US6020616A

公开(公告)日：2000-02-01

申请号：US52908

申请日：1998-03-31

Applicant: Subhas Bothra ,  Paul R. Findley

Inventor： Subhas Bothra ,  Paul R. Findley

IPC: H01L21/762 ,  H01L23/522 ,  H01L27/10 ,  H01L29/00

CPC classification number: H01L27/10 ,  H01L21/76229 ,  H01L23/5222 ,  H01L2924/0002

Abstract: Disclosed is a network of on-chip capacitive structures for suppressing power supply inductive noise, methods for making, and systems for designing the on-chip capacitive structures. The network includes a plurality of dummy active regions that are dispersed throughout an integrated circuit design that has a plurality of active regions. The plurality of dummy active regions are separated from the plurality of active regions by at least a bloat distance. The network further includes a network of dummy polysilicon lines that are configured to overlie selected dummy active regions. The network of dummy polysilcon lines that overlie the selected dummy active regions function as dummy gates. In this embodiment, the selected dummy active regions and the dummy polysilicon lines that overlie the selected dummy active regions form the network of on-chip capacitive structures.

Abstract translation: 公开了用于抑制电源感应噪声的片上电容结构网络，制造方法以及用于设计片上电容结构的系统。 网络包括分散在具有多个有源区域的集成电路设计中的多个虚拟有源区域。 多个虚拟有源区域与多个有源区域分开至少一个膨胀距离。 该网络还包括虚拟多晶硅线路网络，其被配置为覆盖所选择的虚拟有源区域。 覆盖所选择的虚拟有源区域的虚拟聚硅氧烷线的网络用作虚拟门。 在本实施例中，所选择的虚拟有源区和覆盖所选择的虚拟有源区的虚拟多晶硅线形成片上电容结构的网络。