公开(公告)号：US07071517B2

公开(公告)日：2006-07-04

申请号：US10695061

申请日：2003-10-28

申请人： Seong-Ho Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Sung-Min Kim ,  Shin-Ae Lee

发明人： Seong-Ho Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Sung-Min Kim ,  Shin-Ae Lee

IPC分类号： H01L29/41

CPC分类号： H01L21/76831 ,  H01L21/28114 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/42376 ,  H01L2924/0002 ,  H01L2924/00

摘要： A self-aligned contact structure and a method of forming the same include selected neighboring gate electrodes with adjacent sidewalls that are configured to angle toward each other. The angled surfaces of the gate electrodes can be protected using a liner layer that can extend the length of the contact window to define the sidewalls of the contact window.

公开(公告)号：US07002207B2

公开(公告)日：2006-02-21

申请号：US10610607

申请日：2003-07-01

申请人： Sung-Min Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Seong-Ho Kim

发明人： Sung-Min Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Seong-Ho Kim

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/785 ,  H01L21/823412 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/66787 ,  H01L29/78 ,  H01L29/78642 ,  H01L29/78654 ,  H01L29/78696

摘要： Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.

摘要翻译： 集成电路场效应晶体管器件包括在表面上具有表面和有源沟道图案的衬底。 活动通道图案包括彼此堆叠并且彼此间隔开以限定相邻通道之间的至少一个通道的通道。 栅电极围绕通道并延伸穿过至少一个通道。 还提供了一对源极/漏极区域。 通过在衬底的表面上形成预活性图案来制造集成电路场效应晶体管。 预激活图案包括彼此交替堆叠的一系列通道间层和沟道层。 源极/漏极区域在预活化图案的相对端处在衬底上形成。 选择性地去除通道间层以形成隧道。 在隧道中形成栅电极并围绕通道。

公开(公告)号：US06875666B2

公开(公告)日：2005-04-05

申请号：US10458028

申请日：2003-06-09

申请人： Chang-Sub Lee ,  Jeong-Dong Choi ,  Seong-Ho Kim ,  Shin-Ae Lee ,  Sung-Min Kim ,  Dong-Gun Park

发明人： Chang-Sub Lee ,  Jeong-Dong Choi ,  Seong-Ho Kim ,  Shin-Ae Lee ,  Sung-Min Kim ,  Dong-Gun Park

IPC分类号： H01L21/336 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/10

CPC分类号： H01L27/10873 ,  H01L21/26586 ,  H01L21/823412 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/1083

摘要： Transistors of a semiconductor device are fabricated by forming a plurality of gate electrodes on a semiconductor substrate. The gate electrodes are used as an ion implantation mask. A first impurity is ion implanted below the exposed surface of the semiconductor substrate to form first impurity regions. A second impurity is ion implanted in two directions by tilting the implantation to a predetermined angle to thereby form second impurity regions separated from the first impurity regions. The second impurity regions are formed below the channel region under the gate electrodes. The second impurity regions may overlap to provide a higher impurity concentration below a portion of the channel.

摘要翻译： 通过在半导体衬底上形成多个栅电极来制造半导体器件的晶体管。 栅电极用作离子注入掩模。 第一杂质是离子注入到半导体衬底的暴露表面之下以形成第一杂质区。 通过将注入倾斜到预定角度从而将第二杂质离子注入两个方向，从而形成与第一杂质区分离的第二杂质区。 第二杂质区形成在栅极下方的沟道区的下方。 第二杂质区域可以重叠，以在通道的一部分下方提供较高的杂质浓度。

公开(公告)号：US07871914B2

公开(公告)日：2011-01-18

申请号：US12431488

申请日：2009-04-28

申请人： Seong-Ho Kim ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Sung-Min Kim ,  Shin-Ae Lee ,  Dong-Gun Park

发明人： Seong-Ho Kim ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Sung-Min Kim ,  Shin-Ae Lee ,  Dong-Gun Park

IPC分类号： H01L21/336

CPC分类号： H01L29/4983 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/7833 ,  H01L29/7834

摘要： A semiconductor device includes a semiconductor substrate having a recess therein. A gate insulator is disposed on the substrate in the recess. The device further includes a gate electrode including a first portion on the gate insulator in the recess and a second reduced-width portion extending from the first portion. A source/drain region is disposed in the substrate adjacent the recess. The recess may have a curved shape, e.g., may have hemispherical or ellipsoid shape. The source/drain region may include a lighter-doped portion adjoining the recess. Relate fabrication methods are also discussed.

摘要翻译： 半导体器件包括其中具有凹部的半导体衬底。 栅极绝缘体设置在凹部中的基板上。 该器件还包括栅电极，其包括位于凹槽中的栅极绝缘体上的第一部分和从第一部分延伸的第二缩小宽度部分。 源极/漏极区域设置在邻近凹部的衬底中。 凹部可以具有弯曲的形状，例如可以具有半球形或椭球形。 源极/漏极区域可以包括邻近凹部的较轻掺杂部分。 还讨论了相关制造方法。

公开(公告)号：US07541656B2

公开(公告)日：2009-06-02

申请号：US11556352

申请日：2006-11-03

申请人： Seong-Ho Kim ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Sung-Min Kim ,  Shin-Ae Lee ,  Dong-Gun Park

发明人： Seong-Ho Kim ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Sung-Min Kim ,  Shin-Ae Lee ,  Dong-Gun Park

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/4983 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/7833 ,  H01L29/7834

摘要： A semiconductor device includes a semiconductor substrate having a recess therein. A gate insulator is disposed on the substrate in the recess. The device further includes a gate electrode including a first portion on the gate insulator in the recess and a second reduced-width portion extending from the first portion. A source/drain region is disposed in the substrate adjacent the recess. The recess may have a curved shape, e.g., may have hemispherical or ellipsoid shape. The source/drain region may include a lighter-doped portion adjoining the recess. Relate fabrication methods are also discussed.

摘要翻译： 半导体器件包括其中具有凹部的半导体衬底。 栅极绝缘体设置在凹部中的基板上。 该器件还包括栅电极，其包括位于凹槽中的栅极绝缘体上的第一部分和从第一部分延伸的第二缩小宽度部分。 源极/漏极区域设置在邻近凹部的衬底中。 凹部可以具有弯曲的形状，例如可以具有半球形或椭球形。 源极/漏极区域可以包括邻近凹部的较轻掺杂部分。 还讨论了相关制造方法。

公开(公告)号：US20070057288A1

公开(公告)日：2007-03-15

申请号：US11556352

申请日：2006-11-03

申请人： Seong-Ho Kim ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Sung-Min Kim ,  Shin-Ae Lee ,  Dong-Gun Park

发明人： Seong-Ho Kim ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Sung-Min Kim ,  Shin-Ae Lee ,  Dong-Gun Park

IPC分类号： H01L31/00

CPC分类号： H01L29/4983 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/7833 ,  H01L29/7834

摘要： A semiconductor device includes a semiconductor substrate having a recess therein. A gate insulator is disposed on the substrate in the recess. The device further includes a gate electrode including a first portion on the gate insulator in the recess and a second reduced-width portion extending from the first portion. A source/drain region is disposed in the substrate adjacent the recess. The recess may have a curved shape, e.g., may have hemispherical or ellipsoid shape. The source/drain region may include a lighter-doped portion adjoining the recess. Relate fabrication methods are also discussed.

摘要翻译： 半导体器件包括其中具有凹部的半导体衬底。 栅极绝缘体设置在凹部中的基板上。 该器件还包括栅电极，其包括位于凹槽中的栅极绝缘体上的第一部分和从第一部分延伸的第二缩小宽度部分。 源极/漏极区域设置在邻近凹部的衬底中。 凹部可以具有弯曲的形状，例如可以具有半球形或椭球形。 源极/漏极区域可以包括邻近凹部的较轻掺杂部分。 还讨论了相关制造方法。

公开(公告)号：US20060192255A1

公开(公告)日：2006-08-31

申请号：US11396819

申请日：2006-04-03

申请人： Seong-Ho Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Sung-Min Kim ,  Shin-Ae Lee

发明人： Seong-Ho Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Sung-Min Kim ,  Shin-Ae Lee

IPC分类号： H01L29/76

CPC分类号： H01L21/76831 ,  H01L21/28114 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L27/10888 ,  H01L27/10894 ,  H01L29/42376 ,  H01L2924/0002 ,  H01L2924/00

摘要： A self-aligned contact structure and a method of forming the same include selected neighboring gate electrodes with adjacent sidewalls that are configured to angle toward each other. The angled surfaces of the gate electrodes can be protected using a liner layer that can extend the length of the contact window to define the sidewalls of the contact window.

公开(公告)号：US07026688B2

公开(公告)日：2006-04-11

申请号：US11119786

申请日：2005-05-02

申请人： Sung-Min Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Seong-Ho Kim

发明人： Sung-Min Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Seong-Ho Kim

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/785 ,  H01L21/823412 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/66787 ,  H01L29/78 ,  H01L29/78642 ,  H01L29/78654 ,  H01L29/78696

摘要： Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.

公开(公告)号：US20050189583A1

公开(公告)日：2005-09-01

申请号：US11119786

申请日：2005-05-02

申请人： Sung-Min Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Seong-Ho Kim

发明人： Sung-Min Kim ,  Dong-Gun Park ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Shin-Ae Lee ,  Seong-Ho Kim

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76

CPC分类号： H01L29/785 ,  H01L21/823412 ,  H01L29/42356 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/66787 ,  H01L29/78 ,  H01L29/78642 ,  H01L29/78654 ,  H01L29/78696

摘要： Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.

摘要翻译： 集成电路场效应晶体管器件包括在表面上具有表面和有源沟道图案的衬底。 活动通道图案包括彼此堆叠并且彼此间隔开以限定相邻通道之间的至少一个通道的通道。 栅电极围绕通道并延伸穿过至少一个通道。 还提供了一对源极/漏极区域。 通过在衬底的表面上形成预活性图案来制造集成电路场效应晶体管。 预激活图案包括彼此交替堆叠的一系列通道间层和通道层。 源极/漏极区域在预活化图案的相对端处在衬底上形成。 选择性地去除通道间层以形成隧道。 在隧道中形成栅电极并围绕通道。

公开(公告)号：US20090215238A1

公开(公告)日：2009-08-27

申请号：US12431488

申请日：2009-04-28

申请人： Seong-Ho Kim ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Sung-Min Kim ,  Shin-Ae Lee ,  Dong-Gun Park

发明人： Seong-Ho Kim ,  Chang-Sub Lee ,  Jeong-Dong Choe ,  Sung-Min Kim ,  Shin-Ae Lee ,  Dong-Gun Park

IPC分类号： H01L21/336

CPC分类号： H01L29/4983 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/7833 ,  H01L29/7834

摘要： A semiconductor device includes a semiconductor substrate having a recess therein. A gate insulator is disposed on the substrate in the recess. The device further includes a gate electrode including a first portion on the gate insulator in the recess and a second reduced-width portion extending from the first portion. A source/drain region is disposed in the substrate adjacent the recess. The recess may have a curved shape, e.g., may have hemispherical or ellipsoid shape. The source/drain region may include a lighter-doped portion adjoining the recess. Relate fabrication methods are also discussed.

摘要翻译： 半导体器件包括其中具有凹部的半导体衬底。 栅极绝缘体设置在凹部中的基板上。 该器件还包括栅电极，其包括位于凹槽中的栅极绝缘体上的第一部分和从第一部分延伸的第二缩小宽度部分。 源极/漏极区域设置在邻近凹部的衬底中。 凹部可以具有弯曲的形状，例如可以具有半球形或椭球形。 源极/漏极区域可以包括邻近凹部的较轻掺杂部分。 还讨论了相关制造方法。