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    System for defeating erroneous correction in a digital signal reproducing apparatus
    86.
    发明授权
    System for defeating erroneous correction in a digital signal reproducing apparatus 失效
    用于在数字信号再现装置中消除错误校正的系统

    公开(公告)号：US4445216A

    公开(公告)日：1984-04-24

    申请号：US242293

    申请日：1981-03-10

    申请人： Harukuni Kobari ,  Yasuhiro Yamada ,  Susumu Suzuki ,  Chitoshi Hibino

    发明人： Harukuni Kobari ,  Yasuhiro Yamada ,  Susumu Suzuki ,  Chitoshi Hibino

    IPC分类号： G11B20/18 ,  H03M13/00 ,  H03M13/27 ,  G06F11/10

    CPC分类号： G11B20/1809

    摘要： A system for defeating erroneous correction in a digital signal reproducing apparatus. The system includes a reproducing circuit for reproducing a signal sequence in which information words and error correcting words are interleaved. A memory stores the reproduced digital signal sequence and produces a digital signal sequence made up of the information words and error correcting words, which are then de-interleaved and arranged in an original sequence. A correcting circuit corrects adjacent errors with respect to the digital signal sequence produced from the memory. A digital-to-analog converter converts a digital information signal obtained from the correcting circuit into an original analog information signal. The correcting circuit calculates partial syndromes according to predetermined equations and detects the number of erroneous words in one block which is made up of interleaved words. The error correcting operation is stopped when there are certain set of conditions which are related to the values of the partial syndromes and when the number of erroneous words are satisfied. The system continues to stop the correcting operation until other sets of conditions are satisfied, in order to correct errors of up to two words in each of the blocks made up of the de-interleaved words.

    摘要翻译： 一种用于消除数字信号再现装置中的错误校正的系统。 该系统包括用于再现其中信息字和纠错字被交错的信号序列的再现电路。 存储器存储再现的数字信号序列，并产生由信息字和纠错字组成的数字信号序列，然后以原始顺序进行解交织和排列。 校正电路相对于从存储器产生的数字信号序列校正相邻误差。 数模转换器将从校正电路获得的数字信息信号转换为原始模拟信息信号。 校正电路根据预定的方程式计算部分校正子，并检测由交错字组成的一个块中的错误字数。 当存在与部分综合征的值相关的某些条件集合以及满足错误字数时，停止纠错操作。 系统继续停止校正操作，直到满足其他条件为止，以便校正由解交错字组成的每个块中最多两个字的错误。

    Memory control system
    88.
    发明授权
    Memory control system 失效
    内存控制系统

    公开(公告)号：US4333160A

    公开(公告)日：1982-06-01

    申请号：US95553

    申请日：1979-11-19

    申请人： Harukuni Kobari ,  Yasuhiro Yamada ,  Susumu Suzuki ,  Chitoshi Hibino

    发明人： Harukuni Kobari ,  Yasuhiro Yamada ,  Susumu Suzuki ,  Chitoshi Hibino

    IPC分类号： G11B20/18 ,  H04N5/76 ,  G06F13/00

    CPC分类号： G11B20/1809

    摘要： A memory control system comprises a first memory supplied with an incoming modulated digital signal which is formed by subjecting an analog signal to digital signal processing of discontinuous level modulation system, and a first control circuit for supplying a control signal to the first memory. The first control circuit producing the control signal for controlling the first memory in such a manner that the total memory capacity of the first memory is partitioned into a plurality (k) of memory capacity segments having given capacity values (lengths) for use, and the modulated digital signal is written in and further the modulated digital signal thus written in is read out with the order thereof rearranged, interrelatedly with the circulation of addresses through the plurality of divided memory capacity segments while maintaining constant the relationship in terms of capacity values (lengths) between the plurality of divided memory capacity segments.

    摘要翻译： 存储器控制系统包括：第一存储器，其被提供有通过对模拟信号进行不连续电平调制系统的数字信号处理而形成的输入调制数字信号;以及第一控制电路，用于向第一存储器提供控制信号。 第一控制电路产生用于控制第一存储器的控制信号，使得第一存储器的总存储器容量被划分为具有给定容量值（长度）的多个（k）个存储容量段，并且 被调制的数字信号被写入，并且进一步地读出这样写入的调制数字信号，其顺序被重新排列，与通过多个划分的存储器容量段的地址的循环相关联，同时保持在容量值（长度）上的恒定关系 ）在多个划分的存储器容量段之间。

    Watch
    89.
    外观设计
    Watch 失效

    公开(公告)号：USD264056S

    公开(公告)日：1982-04-27

    申请号：US142948

    申请日：1980-04-23

    申请人： Susumu Suzuki

    设计人： Susumu Suzuki