公开(公告)号：US20210351079A1

公开(公告)日：2021-11-11

申请号：US17068037

申请日：2020-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Zhi-Chang Lin ,  Li-Zhen Yu

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: A method of forming a semiconductor transistor device. The method comprises forming a fin-shaped channel structure over a substrate and forming a first source/drain epitaxial structure and a second source/drain epitaxial structure on opposite endings of the fin structure. The method further comprises forming a metal gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain epitaxial structure and the second source/drain epitaxial structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench.

公开(公告)号：US20210336004A1

公开(公告)日：2021-10-28

申请号：US16944263

申请日：2020-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/78

Abstract: A method includes providing a structure having a substrate, a fin, source/drain (S/D) features, an isolation structure adjacent to sidewalls of the fin, one or more channel layers over a first dielectric layer and connecting the S/D features, and a gate structure engaging the one or more channel layers. The method further includes thinning down the structure from its backside until the fin is exposed and selectively etching the fin to form a trench that exposes surfaces of the S/D features, the first dielectric layer, and the isolation structure. The method further includes forming a silicide feature on the S/D features and depositing an inhibitor on the silicide feature but not on the surface of the first dielectric layer and the isolation structure, depositing a dielectric liner layer on the surfaces of the isolation structure and the first dielectric layer but not on the inhibitor, and selectively removing the inhibitor.

公开(公告)号：US20210335783A1

公开(公告)日：2021-10-28

申请号：US16944025

申请日：2020-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsun Chiu ,  Ching-Wei Tsai ,  Yu-Xuan Huang ,  Cheng-Chi Chuang ,  Shang-Wen Chang

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/423 ,  H01L23/535 ,  H01L29/417 ,  H01L29/66 ,  H01L21/768

Abstract: Methods of performing backside etching processes on source/drain regions and gate structures of semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a first interconnect structure on a front-side of the first transistor structure; and a second interconnect structure on a backside of the first transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and first spacers along sidewalls of the contact between the contact and the first dielectric layer, sidewalls of the first spacers facing the first dielectric layer being aligned with sidewalls of the source/drain region of the first transistor structure.

公开(公告)号：US11145728B2

公开(公告)日：2021-10-12

申请号：US16809876

申请日：2020-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/311

Abstract: A method includes forming a gate structure over a fin protruding above a substrate, forming a gate spacer layer on sidewalls of the gate structure, forming an etch stop layer on sidewalls of the gate spacer layer, replacing the gate structure with a gate stack, forming a source/drain contact adjacent the etch stop layer, recessing the gate stack to form a first recess, filling the first recess with a first dielectric material, recessing the source/drain contact and the etch stop layer to form a second recess, filling the second recess with a second dielectric material, recessing the second dielectric material and the gate spacer layer to form a third recess, and filling the third recess with a third dielectric material, wherein the composition of the third dielectric material is different from that of the first dielectric material and the second dielectric material.

公开(公告)号：US20210280454A1

公开(公告)日：2021-09-09

申请号：US16808902

申请日：2020-03-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Cheng-Chi Chuang ,  Chih-Hao Wang ,  Yu-Ming Lin ,  Lin-Yu Huang

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/417 ,  H01L29/66

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a substrate, a first contact layer, and a gate electrode. The first contact layer overlies the substrate and the gate electrode overlies the substrate and is laterally spaced from the first contact layer. A first spacer structure surrounds outermost sidewalls of the first contact layer and separates the gate electrode from the first contact layer. A first hard mask structure is arranged over the first contact layer and is between portions of the first spacer structure. A first contact via extends through the first hard mask structure and contacts the first contact layer. A first liner layer is arranged directly between the first hard mask structure and the first spacer structure.

公开(公告)号：US20210134969A1

公开(公告)日：2021-05-06

申请号：US16809876

申请日：2020-03-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L21/311 ,  H01L29/66

Abstract: A method includes forming a gate structure over a fin protruding above a substrate, forming a gate spacer layer on sidewalls of the gate structure, forming an etch stop layer on sidewalls of the gate spacer layer, replacing the gate structure with a gate stack, forming a source/drain contact adjacent the etch stop layer, recessing the gate stack to form a first recess, filling the first recess with a first dielectric material, recessing the source/drain contact and the etch stop layer to form a second recess, filling the second recess with a second dielectric material, recessing the second dielectric material and the gate spacer layer to form a third recess, and filling the third recess with a third dielectric material, wherein the composition of the third dielectric material is different from that of the first dielectric material and the second dielectric material.

公开(公告)号：US10923424B2

公开(公告)日：2021-02-16

申请号：US16888962

申请日：2020-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Cheng-Chi Chuang ,  Yung-Chih Wang ,  Tien-Lu Lin

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first metal wire arranged within an inter-level dielectric (ILD) layer over a substrate. A second metal wire is arranged within the ILD layer and is laterally separated from the first metal wire by an air-gap. A dielectric layer is arranged over the first metal wire and the second metal wire. The dielectric layer has a curved surface along a top of the air-gap. The curved surface of the dielectric layer is a smooth curved surface that continuously extends between opposing sides of the air-gap. A via is disposed on and over the second metal wire.

公开(公告)号：US20190252319A1

公开(公告)日：2019-08-15

申请号：US16394483

申请日：2019-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Cheng-Chi Chuang ,  Yung-Chih Wang ,  Tien-Lu Lin

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first metal wire arranged within an inter-level dielectric (ILD) layer over a substrate and laterally separated in a first direction from a first closest air-gap by a first distance. A second metal wire is arranged within the ILD layer and is laterally separated in the first direction from a second closest air-gap by a second distance that is larger than the first distance. A via is disposed on an upper surface of the second metal wire.

公开(公告)号：US10276498B2

公开(公告)日：2019-04-30

申请号：US15853021

申请日：2017-12-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Cheng-Chi Chuang ,  Yung-Chih Wang ,  Tien-Lu Lin

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: In some embodiments, the present disclosure relates to an interconnect structure. The interconnect structure has a first dielectric layer disposed over a substrate and a conductive structure arranged within the first dielectric layer. An air-gap separates sidewalls of the conductive structure from the first dielectric layer. The air-gap continuously extends from a first side of the conductive structure to an opposing second side of the conductive structure.

公开(公告)号：US20180090439A1

公开(公告)日：2018-03-29

申请号：US15819280

申请日：2017-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Wei Liu ,  Tai-I Yang ,  Cheng-Chi Chuang ,  Tien-Lu Lin

IPC: H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76838 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure, in some embodiments, relates to an integrated chip having a back-end-of-the-line interconnect stack. The integrated chip has a dielectric structure arranged over a substrate. A first interconnect structure is arranged within the dielectric structure and has sidewalls and a horizontally extending surface that define a recess within a lower surface of the first interconnect structure facing the substrate. A lower interconnect structure is arranged within the dielectric structure and extends from within the recess to a location between the first interconnect structure and the substrate. The first interconnect structure and the lower interconnect structure comprise one or more different conductive materials.