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    Integrated circuits with buried interconnect conductors
    81.
    发明授权
    Integrated circuits with buried interconnect conductors 有权

    公开(公告)号：US11456217B2

    公开(公告)日：2022-09-27

    申请号：US17306633

    申请日：2021-05-03

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuo-Cheng Chiang ,  Shi Ning Ju ,  Kuan-Lun Cheng ,  Chih-Hao Wang

    IPC: H01L21/70 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L27/088

    Abstract: Examples of an integrated circuit with an interconnect structure that includes a buried interconnect conductor and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a substrate that includes a plurality of fins extending from a remainder of the substrate. A spacer layer is formed between the plurality of fins, and a buried interconnect conductor is formed on the spacer layer between the plurality of fins. A set of capping layers is formed on the buried interconnect conductor between the plurality of fins. A contact recess is etched through the set of capping layers that exposes the buried interconnect conductor, and a contact is formed in the contact recess that is electrically coupled to the buried interconnect conductor.

    Backside Vias in Semiconductor Device
    83.
    发明申请
    Backside Vias in Semiconductor Device 有权

    公开(公告)号：US20220278213A1

    公开(公告)日：2022-09-01

    申请号：US17743992

    申请日：2022-05-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

    IPC: H01L29/423 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66

    Abstract: Methods of forming backside vias connected to source/drain regions of long-channel semiconductor devices and short-channel semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a second transistor structure adjacent the first transistor structure; a first interconnect structure on a front-side of the first transistor structure and the second transistor structure; and a second interconnect structure on a backside of the first transistor structure and the second transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a second dielectric layer on the backside of the second transistor structure; a first contact extending through the first dielectric layer and electrically coupled to a first source/drain region of the first transistor structure; and a second contact extending through the second dielectric layer and electrically coupled to a second source/drain region of the second transistor structure, the second contact having a second length less than a first length of the first contact.

    Semiconductor devices with backside contacts and isolation
    85.
    发明授权
    Semiconductor devices with backside contacts and isolation 有权

    公开(公告)号：US11430789B2

    公开(公告)日：2022-08-30

    申请号：US17104351

    申请日：2020-11-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-Yuan Chen ,  Huan-Chieh Su ,  Cheng-Chi Chuang ,  Chih-Hao Wang

    IPC: H01L27/092 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78

    Abstract: A method includes forming a fin structure over a substrate, wherein the fin structure includes a base layer, an isolating layer over the base layer, and a stack of channel layers and first sacrificial layers alternately stacked over the isolating layer. The method further includes forming an isolation structure adjacent to sidewalls of the fin structure, wherein a top surface of the isolation structure is above a bottom surface of the isolating layer and below a top surface of the isolating layer. The method further includes depositing a second sacrificial layer over the isolation structure and over the sidewalls of the fin structure; etching the second sacrificial layer and the fin structure to form two source/drain trenches, wherein the source/drain trenches expose the base layer; partially removing the first and the second sacrificial layers through the source/drain trenches to form gaps; and depositing a dielectric spacer in the gaps.

    Nanosheet device with dipole dielectric layer and methods of forming the same
    90.
    发明授权
    Nanosheet device with dipole dielectric layer and methods of forming the same 有权

    公开(公告)号：US11374105B2

    公开(公告)日：2022-06-28

    申请号：US16835759

    申请日：2020-03-31

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chung-Wei Hsu ,  Kuo-Cheng Chiang ,  Lung-Kun Chu ,  Mao-Lin Huang ,  Jia-Ni Yu ,  Chih-Hao Wang

    IPC: H01L29/51 ,  H01L29/06 ,  H01L21/02 ,  H01L29/66

    Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises first semiconductor layers and second semiconductor layers over a substrate, wherein the first semiconductor layers and the second semiconductor layers are separated and stacked up, and a thickness of each second semiconductor layer is less than a thickness of each first semiconductor layer; a first interfacial layer around each first semiconductor layer; a second interfacial layer around each second semiconductor layer; a first dipole gate dielectric layer around each first semiconductor layer and over the first interfacial layer; a second dipole gate dielectric layer around each second semiconductor layer and over the second interfacial layer; a first gate electrode around each first semiconductor layer and over the first dipole gate dielectric layer; and a second gate electrode around each second semiconductor layer and over the second dipole gate dielectric layer.

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