公开(公告)号：US11107735B2

公开(公告)日：2021-08-31

申请号：US16696121

申请日：2019-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/8238 ,  H01L27/088 ,  H01L29/06 ,  H01L27/092 ,  H01L29/66

Abstract: A method of fabricating a fin-like field effect transistor (FinFET) device includes providing a semiconductor substrate having a region for forming p-type metal-oxide-semiconductor (PMOS) devices and a region for forming n-type metal-oxide-semiconductor (PMOS) devices, forming fin structures in both regions of the substrate separated by isolation features, first forming source/drain (S/D) features in the PMOS region, and subsequently forming S/D features in the NMOS region. First forming the PMOS S/D features and then forming the NMOS S/D features results in a greater extent of loss of isolation features in the PMOS region than in the NMOS region.

公开(公告)号：US11107734B2

公开(公告)日：2021-08-31

申请号：US15830859

申请日：2017-12-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang Lee ,  Feng-Cheng Yang ,  Ting-Yeh Chen

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/308 ,  H01L27/088 ,  H01L29/08

Abstract: A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure and a dielectric layer disposed on an upper surface of the isolation insulating layer. Both the first fin structure and the second fin structure are disposed over the substrate, and extend in a first direction in plan view. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction. The first and second fin structures not covered by the gate structure are recessed below the upper surface of the isolation insulating layer. The source/drain structure is formed over the recessed first and second fin structures. A void is formed between the source/drain structure and the dielectric layer.

公开(公告)号：US20210202733A1

公开(公告)日：2021-07-01

申请号：US17201147

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-An Lin ,  Wei-Yuan Lu ,  Feng-Cheng Yang ,  Tzu-Ching Lin ,  Li-Li Su

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  A61B5/15 ,  G01N1/14 ,  G01N33/49

Abstract: The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.

公开(公告)号：US11018134B2

公开(公告)日：2021-05-25

申请号：US15715310

申请日：2017-09-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Te Lin ,  Wei-Yuan Lu ,  Feng-Cheng Yang

IPC: H01L27/088 ,  H01L29/06 ,  H01L23/48 ,  H01L23/522 ,  H01L27/06 ,  H01L29/66 ,  H01L27/11 ,  H01L49/02 ,  H01L21/8234 ,  H01L27/22 ,  H01L21/8258

Abstract: A semiconductor device is provided. The semiconductor device includes a first transistor, a first interconnect structure, and a second transistor. The first transistor has a first gate length. The first interconnect structure is over the first transistor. The second transistor is over the first interconnect structure. The second transistor is electrically coupled to the first transistor through the first interconnect structure. The second transistor has a second gate length, and the first gate length is shorter than the second gate length.

公开(公告)号：US20210118744A1

公开(公告)日：2021-04-22

申请号：US17111978

申请日：2020-12-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/8238 ,  H01L21/02 ,  H01L27/092 ,  H01L21/311 ,  H01L29/66 ,  H01L29/08 ,  H01L29/161

Abstract: A fin structure of a FinFET device is formed over a substrate. A first layer is formed over the fin structure. A gate layer is formed over the fin structure and over the first layer. The gate layer is patterned into a gate stack that wraps around the fin structure. A second layer is formed over the first layer and over the gate stack. A first etching process is performed to remove portions of the second layer formed over the fin structure, the first layer serves as an etching-stop layer during the first etching process. A second etching process is performed to remove portions of the first layer to expose a portion of the fin structure. A removal of the portions of the first layer does not substantially affect the second layer. A source/drain region is epitaxially grown on the exposed portion of the fin structure.

公开(公告)号：US10950730B2

公开(公告)日：2021-03-16

申请号：US16529357

申请日：2019-08-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-An Lin ,  Wei-Yuan Lu ,  Feng-Cheng Yang ,  Tzu-Ching Lin ,  Li-Li Su

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  A61B5/15 ,  G01N1/14 ,  G01N33/49 ,  H01L29/04

Abstract: The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.

公开(公告)号：US10861753B2

公开(公告)日：2020-12-08

申请号：US16412007

申请日：2019-05-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Bo-Yu Lai ,  Kai-Hsuan Lee ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/336 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/311

Abstract: A method includes forming a gate stack over a semiconductor substrate, forming a first spacer layer on a sidewall of the gate stack, forming a sacrificial spacer film over the first spacer layer, forming an epitaxy structure on the semiconductor substrate, and performing an etching process on the sacrificial spacer film to form a gap between the first spacer layer and the epitaxy structure. An outer portion of the sacrificial spacer film has a topmost end higher than that of an inner portion of the sacrificial spacer film after performing the etching process. The method further includes forming a second spacer layer to seal the gap between the epitaxy structure and the first spacer layer.

公开(公告)号：US10861749B2

公开(公告)日：2020-12-08

申请号：US16599912

申请日：2019-10-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chen ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  H01L27/092 ,  H01L21/311 ,  H01L29/08 ,  H01L29/161

Abstract: A fin structure of a FinFET device is formed over a substrate. A first layer is formed over the fin structure. A gate layer is formed over the fin structure and over the first layer. The gate layer is patterned into a gate stack that wraps around the fin structure. A second layer is formed over the first layer and over the gate stack. A first etching process is performed to remove portions of the second layer formed over the fin structure, the first layer serves as an etching-stop layer during the first etching process. A second etching process is performed to remove portions of the first layer to expose a portion of the fin structure. A removal of the portions of the first layer does not substantially affect the second layer. A source/drain region is epitaxially grown on the exposed portion of the fin structure.

公开(公告)号：US20200251594A1

公开(公告)日：2020-08-06

申请号：US16853280

申请日：2020-04-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yang Lee ,  Tzu-Hsiang Hsu ,  Ting-Yeh Chen ,  Feng-Cheng Yang

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/11 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66

Abstract: A semiconductor structure includes a substrate, first fins extending from the substrate with a first fin pitch, and second fins extending from the substrate with a second fin pitch that is smaller than the first fin pitch. The semiconductor structure also includes first gate structures engaging the first fins, second gate structures engaging the second fins, first epitaxial semiconductor features adjacent the first gate structures, and second epitaxial semiconductor features adjacent the second gate structures. The first epitaxial semiconductor features are partially embedded in the first fins at a first depth, and the second epitaxial semiconductor features are partially embedded in the second fins at a second depth that is smaller than the first depth.

公开(公告)号：US10714619B2

公开(公告)日：2020-07-14

申请号：US16046740

申请日：2018-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yang Lee ,  Chia-Chun Lan ,  Chia-Ling Chan ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/311 ,  H01L29/78 ,  H01L29/161 ,  H01L29/08 ,  H01L29/167 ,  H01L29/66 ,  H01L27/092 ,  H01L21/8238

Abstract: A method for fabricating a semiconductor device includes forming a doped semiconductor layer on a substrate and forming a fin structure disposed on the doped semiconductor layer. The fin structure is doped with a p-type dopant. The method further includes forming a source/drain region within an upper portion of the fin structure and forming a fin sidewall along a lower portion of the fin structure. The fin sidewall has the p-type dopant.