公开(公告)号：US20220375944A1

公开(公告)日：2022-11-24

申请号：US17871764

申请日：2022-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Chih-Chuan Yang ,  Hsin-Wen Su ,  Kian-Long Lim ,  Chien-Chih Lin

IPC: H01L27/11 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  G11C11/412

Abstract: An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surface of the first spacer structure to the first sidewall. A P-type metal oxide semiconductor (PMOS) transistor includes a second gate and a second spacer structure disposed on a second sidewall of the second gate in the first direction and measured from an outermost point of an outer surface of the second spacer structure to the second sidewall. The second spacer structure has a second thickness that is greater than the first thickness. The NMOS transistor is a pass-gate of a static random access memory (SRAM) cell, and the PMOS transistor is a pull-up of the SRAM cell.

公开(公告)号：US11508738B2

公开(公告)日：2022-11-22

申请号：US17036487

申请日：2020-09-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Chih-Chuan Yang ,  Hsin-Wen Su ,  Kian-Long Lim ,  Chien-Chih Lin

IPC: H01L27/11 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  G11C11/412

Abstract: An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surface of the first spacer structure to the first sidewall. A P-type metal oxide semiconductor (PMOS) transistor includes a second gate and a second spacer structure disposed on a second sidewall of the second gate in the first direction and measured from an outermost point of an outer surface of the second spacer structure to the second sidewall. The second spacer structure has a second thickness that is greater than the first thickness. The NMOS transistor is a pass-gate of a static random access memory (SRAM) cell, and the PMOS transistor is a pull-up of the SRAM cell.

公开(公告)号：US20220359308A1

公开(公告)日：2022-11-10

申请号：US17815085

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Tzu-Hsiang Hsu ,  Chong-De Lien ,  Szu-Chi Yang ,  Hsin-Wen Su ,  Chih-Hsiang Huang

IPC: H01L21/8238 ,  H01L21/306 ,  H01L27/11

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method comprises forming first and second semiconductor fins in first and second regions of a substrate, respectively; forming first and second dummy gate stacks over the first and second semiconductor fins, respectively, and forming a spacer layer over the first and the second dummy gate stacks; forming a first pattern layer with a thickness along the spacer layer in the first region; form a first source/drain (S/D) trench along the first pattern layer and epitaxially growing a first epitaxial feature therein; removing the first pattern layer to expose the spacer layer; forming a second pattern layer with a different thickness along the spacer layer in the second region; form a second S/D trench along the second pattern layer and epitaxially growing a second epitaxial feature therein; and removing the second pattern layer to expose the spacer layer.

公开(公告)号：US20220352181A1

公开(公告)日：2022-11-03

申请号：US17813782

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Chia-Hao Pao ,  Yu-Kuan Lin ,  Lien-Jung Hung ,  Ping-Wei Wang ,  Shih-Hao Lin

IPC: H01L27/11 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.

公开(公告)号：US20220319583A1

公开(公告)日：2022-10-06

申请号：US17843241

申请日：2022-06-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Shih-Hao Lin

IPC: G11C11/412 ,  H01L21/475 ,  H01L27/11 ,  G11C11/419

Abstract: Semiconductor devices and methods are provided. A semiconductor device of the present disclosure includes a bias source, a memory cell array including a first region adjacent to the bias source and a second region away from the bias source, and a conductive line electrically coupled to the bias source, a first memory cell in the first region and a second memory cell in the second region. The first memory cell is characterized by a first alpha ratio and the second memory cell is characterized by a second alpha ratio smaller than the first alpha ratio.

公开(公告)号：US11462549B2

公开(公告)日：2022-10-04

申请号：US16916150

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chong-De Lien ,  Shih-Hao Lin

IPC: H01L27/11 ,  H01L29/775 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

Abstract: Provided is a SRAM device including a pull-up device and a pull-down device. The pull-up device includes a plurality of first epitaxial source and drain (S/D) features on a first fin, and a plurality of first residues between the plurality of first epitaxial source and drain (S/D) features and the first fin. The pull-down device includes a plurality of second epitaxial S/D features on a second fin.

公开(公告)号：US11342338B2

公开(公告)日：2022-05-24

申请号：US17009034

申请日：2020-09-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Hao Lin ,  Kian-Long Lim ,  Chih-Chuan Yang ,  Chia-Hao Pao ,  Jing-Yi Lin

IPC: H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8238 ,  H01L29/66

Abstract: A substrate includes a first doped region having a first type dopant, and a second doped region having a second type dopant and adjacent to the first doped region. A stack is formed that includes first layers and second layers alternating with each other. The first and second layers each have a first and second semiconductor material, respectively. The second semiconductor material is different than the first semiconductor material. A mask element is formed that has an opening in a channel region over the second doped region. A top portion of the stack not covered by the mask element is recessed. The stack is then processed to form a first and a second transistors. The first transistor has a first number of first layers. The second transistor has a second number of first layers. The first number is greater than the second number.

公开(公告)号：US20220037340A1

公开(公告)日：2022-02-03

申请号：US16945146

申请日：2020-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chuan Yang ,  Chia-Hao Pao ,  Yu-Kuan Lin ,  Lien Jung Hung ,  Ping-Wei Wang ,  Shih-Hao Lin

IPC: H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.

公开(公告)号：US20210408010A1

公开(公告)日：2021-12-30

申请号：US16916150

申请日：2020-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chong-De Lien ,  Shih-Hao Lin

IPC: H01L27/11 ,  H01L29/775 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66

Abstract: Provided is a SRAM device including a pull-up device and a pull-down device. The pull-up device includes a plurality of first epitaxial source and drain (S/D) features on a first fin, and a plurality of first residues between the plurality of first epitaxial source and drain (S/D) features and the first fin. The pull-down device includes a plurality of second epitaxial S/D features on a second fin.

公开(公告)号：US20210313463A1

公开(公告)日：2021-10-07

申请号：US17352587

申请日：2021-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Wen Su ,  Yu-Kuan Lin ,  Chih-Chuan Yang ,  Chang-Ta Yang ,  Shih-Hao Lin

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/762

Abstract: A semiconductor device comprises a memory macro including a well pick-up (WPU) area oriented lengthwise along a first direction, and memory bit areas adjacent to the WPU area. In the WPU area, the memory macro includes n-type and p-type wells arranged alternately along the first direction with well boundaries between adjacent wells; gate structures over the wells and oriented lengthwise along the first direction; a first dielectric layer disposed at each of the well boundaries; first contact features disposed over one of the p-type wells; and second contact features disposed over one of the n-type wells. From a top view, the first dielectric layer extends along a second direction perpendicular to the first direction and separates all the gate structures in the first WPU area, the first contact features are disposed between the gate structures, and the second contact features are disposed between the gate structures.