公开(公告)号：US20200152772A1

公开(公告)日：2020-05-14

申请号：US16746097

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ju-Li Huang ,  Chun-Sheng Liang ,  Ming-Chi Huang ,  Ming-Hsi Yeh ,  Ying-Liang Chuang ,  Hsin-Che Chiang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/78

Abstract: Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.

公开(公告)号：US10541317B2

公开(公告)日：2020-01-21

申请号：US15909847

申请日：2018-03-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ju-Li Huang ,  Chun-Sheng Liang ,  Ming-Chi Huang ,  Ming-Hsi Yeh ,  Ying-Liang Chuang ,  Hsin-Che Chiang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8234 ,  H01L21/321 ,  H01L21/3105 ,  H01L21/02 ,  H01L21/027

Abstract: Methods for, and structures formed by, wet process assisted approaches implemented in a replacement gate process are provided. Generally, in some examples, a wet etch process for removing a capping layer can form a first monolayer on the underlying layer as an adhesion layer and a second monolayer on, e.g., an interfacial dielectric layer between a gate spacer and a fin as an etch protection mechanism. Generally, in some examples, a wet process can form a monolayer on a metal layer, like a barrier layer of a work function tuning layer, as a hardmask for patterning of the metal layer.

公开(公告)号：US20190304834A1

公开(公告)日：2019-10-03

申请号：US15939025

申请日：2018-03-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu Shih Wang ,  Shian Wei Mao ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L21/768 ,  H01L23/522

Abstract: In one exemplary aspect, a method comprises providing a semiconductor structure having a substrate, one or more first dielectric layers over the substrate, a first metal plug in the one or more first dielectric layers, and one or more second dielectric layers over the one or more first dielectric layers and the first metal plug. The method further comprises etching a via hole into the one or more second dielectric layers to expose the first metal plug, etching a top surface of the first metal plug to create a recess thereon, and applying a metal corrosion protectant comprising a metal corrosion inhibitor to the top surface of the first metal plug.

公开(公告)号：US10361133B2

公开(公告)日：2019-07-23

申请号：US15707990

申请日：2017-09-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ju-Li Huang ,  Chih-Long Chiang ,  Ying-Liang Chuang ,  Ming-Hsi Yeh ,  Kuo Bin Huang

IPC: H01L21/8238 ,  H01L29/51 ,  H01L27/088 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/02 ,  H01L21/3105

Abstract: Embodiments of the present disclosure provide wet process based methods for modifying threshold value (Vt) of high-k metal gate using self-assembled monolayer (SAM) on dedicated transistor. In one embodiment, the method includes forming a gate structure over a substrate, the gate structure comprising a gate dielectric layer, a barrier layer formed over the gate dielectric layer, and an oxide layer formed over the barrier layer, and forming a self-assembled monolayer on the oxide layer by exposing the oxide layer to an aqueous solution containing metal oxides in a metal dissolving acid.