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117 条记录 (耗时 0.04 秒)

    Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them
    82.
    发明授权
    Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them 失效
    门电路和半导体电路来处理使用它们制造的低振幅信号，存储器，处理器和信息处理系统

    公开(公告)号：US5677641A

    公开(公告)日：1997-10-14

    申请号：US423378

    申请日：1995-04-18

    申请人： Yoji Nishio ,  Kosaku Hirose ,  Hideo Hara ,  Katsunori Koike ,  Kayoko Nemoto ,  Tatsumi Yamauchi ,  Fumio Murabayashi ,  Hiromichi Yamada

    发明人： Yoji Nishio ,  Kosaku Hirose ,  Hideo Hara ,  Katsunori Koike ,  Kayoko Nemoto ,  Tatsumi Yamauchi ,  Fumio Murabayashi ,  Hiromichi Yamada

    IPC分类号： G11C11/41 ,  H03K3/3565 ,  H03K19/0185 ,  H03K19/0948

    CPC分类号： H03K3/3565 ,  H03K19/018521

    摘要： The object of the present invention is to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor. When input signal is supplied through the NMOS pass transistor, said input signal is input to the gate of the first NMOS transistor, and at the same time, is input into the gate of the first PMOS transistor which performs complementary operation with said first NMOS transistor through the second NMOS transistor; said first PMOS gate is connected to the power supply potential through the second PMOS transistor, and the gate of the said second NMOS transistor is connected to the power supply potential; wherein the gate of the said second PMOS transistor gate is controlled by the signal which is connected with both the drain of the said first NMOS transistor and the drain of the said first PMOS transistor.

    摘要翻译： 本发明的目的是提供一种半导体集成电路器件，其中使得输入信号具有低幅度以缩短输入信号的转换时间，所述集成电路器件以低功耗工作，而不流过突破电流 尽管输入具有低幅度操作的输入信号，并且所述集成电路器件包括门电路，存储器和处理器。 当通过NMOS传输晶体管提供输入信号时，所述输入信号被输入到第一NMOS晶体管的栅极，并且同时被输入到与所述第一NMOS晶体管执行互补操作的第一PMOS晶体管的栅极 通过第二NMOS晶体管; 所述第一PMOS栅极通过第二PMOS晶体管连接到电源电位，并且所述第二NMOS晶体管的栅极连接到电源电位; 其中所述第二PMOS晶体管栅极的栅极由与所述第一NMOS晶体管的漏极和所述第一PMOS晶体管的漏极连接的信号控制。

    Arithmetic unit capable of performing concurrent operations for high speed operation
    84.
    发明授权
    Arithmetic unit capable of performing concurrent operations for high speed operation 失效
    算术单元能够执行高速运行的并发操作

    公开(公告)号：US5408426A

    公开(公告)日：1995-04-18

    申请号：US037654

    申请日：1993-03-17

    申请人： Hidehito Takewa ,  Hiromichi Yamada ,  Takashi Hotta ,  Kotaro Shimamura

    发明人： Hidehito Takewa ,  Hiromichi Yamada ,  Takashi Hotta ,  Kotaro Shimamura

    IPC分类号： G06F7/50 ,  G06F7/52 ,  G06F7/535 ,  G06F7/537 ,  G06F7/57 ,  G06F7/38

    CPC分类号： G06F7/535 ,  G06F7/483 ,  G06F7/485 ,  G06F7/5375 ,  G06F7/4873 ,  G06F7/49936 ,  G06F7/49957

    摘要： An arithmetic unit which accepts two numerical values and executes an operation by the use of the two numerical values has an adder-subtracter for executing an addition or a subtraction on the basis of two numerical values obtained directly or indirectly from the accepted two numerical values; a normalizer for executing a normalizing process in which a mantissa part of an added or subtracted result is shifted so that a high-order digit having been developed anew in the result may come to a predetermined position, and in which an exponent part of the result is corrected in accordance with the number of shift places in the shift of the mantissa part; and a rounding device for executing a rounding process in which, on condition that the mantissa part of the added or subtracted result exceeds a predetermined number of digits, the number of digits of the mantissa part is reduced in conformity with a rounding mode designated beforehand. The rounding device executes at least part of the rounding process by the use of the numerical values not yet subjected to the normalizing process, in parallel with the execution of the adder-subtracter or the normalizer.

    摘要翻译： 接受两个数值并通过使用两个数值执行操作的算术单元具有加法器 - 减法器，用于基于从接受的两个数值直接或间接获得的两个数值来执行加法或减法运算; 用于执行归一化处理的归一化器，其中相加或相减结果的尾数部分被移位，使得在结果中重新显现的高阶数字可以到达预定位置，并且其中结果的指数部分 根据尾数部分的偏移位置的数量进行校正; 以及用于执行舍入处理的舍入装置，其中，在相加或相减结果的尾数部分超过预定数量的数字的条件下，尾数部分的位数根据预先指定的舍入模式而减少。 舍入装置与加法器 - 减法器或归一化器的执行并行，通过使用尚未进行归一化处理的数值来执行舍入处理的至少一部分。

    Computer system including an interrupt controller
    90.
    发明授权
    Computer system including an interrupt controller 有权
    计算机系统包括一个中断控制器

    公开(公告)号：US08589612B2

    公开(公告)日：2013-11-19

    申请号：US13106788

    申请日：2011-05-12

    申请人： Hiromichi Yamada ,  Kotaro Shimamura ,  Nobuyasu Kanekawa ,  Yuichi Ishiguro

    发明人： Hiromichi Yamada ,  Kotaro Shimamura ,  Nobuyasu Kanekawa ,  Yuichi Ishiguro

    IPC分类号： G06F13/24

    CPC分类号： G06F13/24 ,  G06F11/1641 ,  G06F2201/845

    摘要： A computer system which shortens standby time of CPUs and improves CPU processing efficiency of a performance mode upon switching from the performance mode (parallel operation) to a safety mode (master/checker operation) is provided. In a computer system including: at least two CPUs; a programmable interrupt controller for interrupting the CPUs; and a comparator for mutually comparing outputs of the CPUs, switching between the performance mode of executing mutually different processes by the CPUs, respectively, to improve performance and the safety mode of executing mutually the same processes by the CPUs and collating results by the comparator to detect failure can be carried out; CPUs to be interrupted can be set for each interrupt factor; and whether the performance mode is to be executed or the safety mode is to be executed can be set for each interrupt factor.

    摘要翻译： 提供一种缩短CPU的待机时间并提高从性能模式（并行操作）切换到安全模式（主/检测器操作）时的CPU处理效率的计算机系统。 在一个计算机系统中，包括：至少两个CPU; 用于中断CPU的可编程中断控制器; 以及比较器，用于相互比较CPU的输出，分别由CPU执行相互不同的处理的性能模式之间进行切换，以提高CPU的性能和执行相同处理的安全模式，并将比较器的结果进行比较 检测失败可以进行; 可以为每个中断因子设置要中断的CPU; 并且可以针对每个中断因子来设置执行性能模式还是执行安全模式。