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117 条记录 (耗时 0.038 秒)

    Semiconductor memory device capable of correcting a read level properly
    81.
    发明授权
    Semiconductor memory device capable of correcting a read level properly 有权
    能够正确地校正读取电平的半导体存储器件

    公开(公告)号：US07525839B2

    公开(公告)日：2009-04-28

    申请号：US11753143

    申请日：2007-05-24

    申请人： Noboru Shibata ,  Hiroshi Sukegawa

    发明人： Noboru Shibata ,  Hiroshi Sukegawa

    IPC分类号： G11C7/10

    CPC分类号： G11C16/0483 ,  G11C11/5642 ,  G11C16/12 ,  G11C16/26 ,  G11C16/3418 ,  G11C2211/5646 ,  G11C2211/565

    摘要： In a memory cell array, a plurality of memory cells each of which stores a plurality of bits are connected to a plurality of word lines and a plurality of bit lines and are arranged in a matrix. Control portions read a threshold level of a second memory cell adjacent to a first memory cell in the memory cell array, determine a correction level according to the threshold level read from the second memory cell, add the determined correction level to a read level of the first memory cell, and then read the threshold level of the first memory cell. A storage portion stores the correction level.

    摘要翻译： 在存储单元阵列中，存储多个位的多个存储单元被连接到多个字线和多个位线并且以矩阵形式排列。 控制部分读取与存储单元阵列中的第一存储器单元相邻的第二存储单元的阈值电平，根据从第二存储器单元读取的阈值电平确定校正电平，将所确定的校正电平加到读出电平 第一存储器单元，然后读取第一存储器单元的阈值电平。 存储部存储校正等级。

    PERSON AUTHENTICATION APPARATUS AND PERSON AUTHENTICATION METHOD
    82.
    发明申请
    PERSON AUTHENTICATION APPARATUS AND PERSON AUTHENTICATION METHOD 审中-公开
    人员认证装置和人员认证方法

    公开(公告)号：US20090087041A1

    公开(公告)日：2009-04-02

    申请号：US12243360

    申请日：2008-10-01

    申请人： Mitsutake Hasebe ,  Hiroshi Sukegawa

    发明人： Mitsutake Hasebe ,  Hiroshi Sukegawa

    IPC分类号： G06K9/00

    CPC分类号： G06K9/00228

    摘要： A face authentication apparatus includes a high tone image acquiring section, a tone converting section, a face characteristic extracting section and a face collation section. The high tone image acquiring section acquires a high tone image containing the face of a walker. The tone converting section converts the acquired high tone image to a low tone image by tone conversion processing which optimizes the brightness of a face area in the high tone image acquired by the high tone image acquiring section. The face characteristic extracting section executes an extraction processing for the face characteristic information based on the low tone image whose brightness is optimized by the tone converting section. Further, the face collation section executes face collation processing based on the low tone image whose brightness is optimized by the tone converting section.

    摘要翻译： 面部认证装置包括高色调图像获取部分，色调转换部分，面部特征提取部分和面部对照部分。 高音图像获取部分获取包含步行者脸部的高音图像。 色调转换部分通过色调转换处理将获得的高色调图像转换成低色调图像，该处理优化由高色调图像获取部分获取的高色调图像中的面部区域的亮度。 面部特征提取部基于由色调变换部优化亮度的低色调图像，对面部特征信息进行提取处理。 此外，脸部对照部分基于由色调转换部分优化亮度的低色调图像来执行面部对照处理。

    Semiconductor memory device which prevents destruction of data
    84.
    发明授权
    Semiconductor memory device which prevents destruction of data 有权
    防止数据破坏的半导体存储器件

    公开(公告)号：US07394691B2

    公开(公告)日：2008-07-01

    申请号：US11498142

    申请日：2006-08-03

    申请人： Noboru Shibata ,  Hiroshi Sukegawa

    发明人： Noboru Shibata ,  Hiroshi Sukegawa

    IPC分类号： G11C11/34 ,  G11C7/00 ,  G11C29/00

    CPC分类号： G11C11/5642 ,  G11C11/5628 ,  G11C16/0483

    摘要： A plurality of memory cells each storing n values (n is a natural number which is not smaller than 3) are arranged in a matrix form in a memory cell array, and each memory cell is connected with a word line and a bit line. Each memory cell stores the n-valued data by a first write operation and a second write operation. A read section sets a potential of a word line, and reads data from a memory cell in the memory cell array. If data read by the read section and written in the second write operation includes an uncorrectable error, a control section changes a potential of a word line supplied to the read section when reading data written in the first write operation.

    摘要翻译： 每个存储n个值的多个存储单元（n是不小于3的自然数）以矩阵形式布置在存储单元阵列中，并且每个存储单元与字线和位线连接。 每个存储单元通过第一写操作和第二写操作来存储n值数据。 读取部分设置字线的电位，并从存储器单元阵列中的存储单元读取数据。 如果由读取部分读取并写入第二写入操作的数据包括不可校正的错误，则当读取在第一写入操作中写入的数据时，控制部分改变提供给读取部分的字线的电位。

    NONVOLATILE MEMORY SYSTEM, AND DATA READ/WRITE METHOD FOR NONVOLATILE MEMORY SYSTEM
    86.
    发明申请
    NONVOLATILE MEMORY SYSTEM, AND DATA READ/WRITE METHOD FOR NONVOLATILE MEMORY SYSTEM 有权
    非易失性存储器系统，以及用于非易失性存储器系统的数据读/写方法

    公开(公告)号：US20080028131A1

    公开(公告)日：2008-01-31

    申请号：US11611607

    申请日：2006-12-15

    申请人： Yasuo Kudo ,  Hiroshi Sukegawa ,  Kazuya Kawamoto

    发明人： Yasuo Kudo ,  Hiroshi Sukegawa ,  Kazuya Kawamoto

    IPC分类号： G06F12/00

    CPC分类号： G11C16/10

    摘要： A nonvolatile memory system comprises a nonvolatile memory having a plurality of data areas; and a memory controller operative to control read and write operations to the nonvolatile memory. The memory controller successively executes read/write operations to plural sectors within a selected data area in the nonvolatile memory in accordance with a command and a sector count and sector address fed from a host device.

    摘要翻译： 非易失性存储器系统包括具有多个数据区域的非易失性存储器; 以及存储器控制器，用于控制对所述非易失性存储器的读取和写入操作。 存储器控制器根据从主机设备馈送的命令和扇区计数和扇区地址，依次对非易失性存储器中所选数据区域内的多个扇区执行读/写操作。

    Memory card and semiconductor device
    87.
    发明申请
    Memory card and semiconductor device 有权
    存储卡和半导体器件

    公开(公告)号：US20050281089A1

    公开(公告)日：2005-12-22

    申请号：US11138521

    申请日：2005-05-27

    申请人： Hiroshi Sukegawa

    发明人： Hiroshi Sukegawa

    IPC分类号： G11C7/00 ,  G11C16/26

    CPC分类号： G11C16/26

    摘要： A semiconductor device includes an interface which executes an interfacing process with a semiconductor memory, and a circuit which performs control to write serial data to the semiconductor memory while skipping a position of a defective column on the semiconductor memory.

    摘要翻译： 半导体器件包括执行与半导体存储器的接口处理的接口，以及执行控制以在跨越半导体存储器上的缺陷列的位置跳过时向半导体存储器写入串行数据的电路。

    Microprocessor boot-up controller, nonvolatile memory controller, and information processing system
    88.
    发明申请
    Microprocessor boot-up controller, nonvolatile memory controller, and information processing system 有权
    微处理器启动控制器，非易失性存储器控制器和信息处理系统

    公开(公告)号：US20050223211A1

    公开(公告)日：2005-10-06

    申请号：US11084039

    申请日：2005-03-21

    申请人： Hiroshi Sukegawa ,  Kenji Sakaue ,  Hitoshi Tsunoda

    发明人： Hiroshi Sukegawa ,  Kenji Sakaue ,  Hitoshi Tsunoda

    IPC分类号： G06F11/10 ,  G06F9/00 ,  G06F9/445 ,  G06F12/00 ,  G06F12/02

    CPC分类号： G11C11/5642 ,  G06F9/4403 ,  G11C16/0483 ,  G11C16/20 ,  G11C29/74 ,  G11C2211/5641

    摘要： The present invention enables a CPU to access a SRAM in the shortest time in sync with the SRAM's ready timing, resulting in a reduction of avarage system boot-up time. The present invention is a processor boot-up controller that includes: volatile memory, which is connected to nonvolatile memory; a selector, which transfers boot-up codes to the volatile memory from the nonvolatile memory; a controller for the nonvolatile memory which is configured from a boot-up control sequencer, which transmits CPU read-in data to the CPU and brings the CPU into a wait state until boot-up code transfer completes; and an error detection and correction unit; is connected to the external CPU and the nonvolatile memory, and boot-up controls the CPU by reading data from the nonvolatile memory. The present invention is an information processing system using a controller for nonvolatile memory, a microprocessor boot-up controller, and multi-valued nonvolatile memory.

    摘要翻译： 本发明使得CPU能够在SRAM的就绪定时同步的最短时间内访问SRAM，从而减少了系统启动时间。 本发明是一种处理器启动控制器，其包括：易失性存储器，其连接到非易失性存储器; 选择器，其将启动代码从非易失性存储器传送到易失性存储器; 用于非易失性存储器的控制器，其由引导控制定序器配置，其将CPU读入数据发送到CPU并使CPU进入等待状态，直到引导代码传送完成; 和错误检测和校正单元; 连接到外部CPU和非易失性存储器，并通过从非易失性存储器读取数据启动控制CPU。 本发明是使用非易失性存储器的控制器，微处理器启动控制器和多值非易失性存储器的信息处理系统。

    Memory system
    89.
    发明授权
    Memory system 有权
    内存系统

    公开(公告)号：US06446177B1

    公开(公告)日：2002-09-03

    申请号：US09407168

    申请日：1999-09-28

    申请人： Yoshiyuki Tanaka ,  Hiroshi Nakamura ,  Hiroshi Sukegawa ,  Mikito Nakabayashi ,  Kazuya Kawamoto

    发明人： Yoshiyuki Tanaka ,  Hiroshi Nakamura ,  Hiroshi Sukegawa ,  Mikito Nakabayashi ,  Kazuya Kawamoto

    IPC分类号： G06F1214

    CPC分类号： G06F12/1433 ,  G06F21/10 ,  G06F21/79

    摘要： In a memory system using a removable recording medium and data stored in the recording medium, identifying information for identifying each recording medium from others is held in the recording medium, and when data stored in the recording medium is used, the identifying information of the recording medium is required. As a result, when a flash memory card, etc. is used, a copyright is reliably protected.

    摘要翻译： 在使用可移动记录介质的存储器系统和存储在记录介质中的数据的情况下，将用于从其他记录介质识别的识别信息保存在记录介质中，并且当使用存储在记录介质中的数据时，记录的识别信息 需要介质 结果，当使用闪存卡等时，版权被可靠地保护。

    Alternative flash EEPROM semiconductor memory system
    90.
    发明授权
    Alternative flash EEPROM semiconductor memory system 失效
    替代闪存EEPROM半导体存储器系统

    公开(公告)号：US5812814A

    公开(公告)日：1998-09-22

    申请号：US200968

    申请日：1994-02-24

    申请人： Hiroshi Sukegawa

    发明人： Hiroshi Sukegawa

    IPC分类号： G06F3/06 ,  G11C16/10 ,  G06F12/16

    CPC分类号： G06F3/0601 ,  G11C16/102 ,  G06F2003/0694 ,  G06F2212/2022

    摘要： A semiconductor memory system including a flash EEPROM comprises a first flash EEPROM included in the first memory drive, a second flash EEPROM included in the second memory drive, and means for controlling access to the first and second flash EEPROMs. The access controlling means includes an address converting means for converting a logical address from a host system into a physical address, according to first and second file management information which indicates correspondence between logical addresses and physical addresses of the first and second memory drives, respectively. The access controlling means further includes memory accessing means, coupled to each of the first and second flash EEPROMs, for accessing a selected EEPROM according to the physical address from the address converting means.

    摘要翻译： 包括快闪EEPROM的半导体存储器系统包括包括在第一存储器驱动器中的第一闪存EEPROM，包括在第二存储器驱动器中的第二快闪EEPROM，以及用于控制对第一和第二闪存EEPROM的访问的装置。 访问控制装置包括地址转换装置，用于根据分别指示第一和第二存储器驱动器的逻辑地址和物理地址之间的对应关系的第一和第二文件管理信息将主机系统的逻辑地址转换为物理地址。 访问控制装置还包括耦合到第一和第二闪存EEPROM中的每一个的存储器访问装置，用于根据来自地址转换装置的物理地址访问所选择的EEPROM。