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公开(公告)号：US20100061132A1
公开(公告)日：2010-03-11
申请号：US12516690
申请日：2006-12-07
CPC分类号： H01L45/144 , G11C13/0004 , G11C13/0069 , G11C2213/75 , H01L27/2436 , H01L27/2463 , H01L27/2472 , H01L45/06 , H01L45/1233
摘要： In a semiconductor storage device such as a phase change memory, a technique which can realize high integration is provided. The semiconductor storage device includes a phase change thin film 101 having two stable phases of a crystal state with low electric resistance and an amorphous state with high electric resistance, upper plug electrodes 102 and 103 provided on one side of the phase change thin film 101, a lower electrode 104 provided on the other side of the phase change thin film 101, a selecting transistor 114 whose drain/source terminals are connected to the upper plug electrode 102 and the lower electrode 104, and a selecting transistor 115 whose drain/source terminals are connected to the upper plug electrode 103 and the lower electrode 104, and a first memory cell is configured with the selecting transistor 114 and a phase change region 111 in the phase change thin film 101 sandwiched between the upper plug electrode 102 and the lower electrode 104, and a second memory cell is configured with the selecting transistor 115 and a phase change region 112 in the phase change thin film 101 sandwiched between the upper plug electrode 103 and the lower electrode 104.
摘要翻译： 在诸如相变存储器的半导体存储装置中，提供了可以实现高集成度的技术。 半导体存储装置包括：具有低电阻的晶体状态的两个稳定相和具有高电阻的非晶态的相变薄膜101，设置在相变薄膜101一侧的上部插塞电极102和103， 设置在相变薄膜101的另一侧的下部电极104，漏极/源极端子连接到上部插塞电极102和下部电极104的选择晶体管114，以及选择晶体管115，其漏极/源极端子 连接到上插头电极103和下电极104，并且第一存储单元配置有夹在上插头电极102和下电极之间的相变薄膜101中的选择晶体管114和相变区域111 104，并且第二存储单元配置有夹在b中的相变薄膜101中的选择晶体管115和相变区域112 在上塞电极103和下电极104之间。
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公开(公告)号：US07542347B2
公开(公告)日：2009-06-02
申请号：US11873254
申请日：2007-10-16
申请人： Satoru Hanzawa , Takeshi Sakata
发明人： Satoru Hanzawa , Takeshi Sakata
IPC分类号： G11C16/04
CPC分类号： G11C29/787 , G11C7/14 , G11C11/1673 , G11C11/1693
摘要： A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.
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公开(公告)号：US20080121860A1
公开(公告)日：2008-05-29
申请号：US12007851
申请日：2008-01-16
CPC分类号： H01L27/2454 , G11C13/0004 , G11C2213/79 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.
摘要翻译： 半导体存储单元及其形成方法利用垂直选择晶体管来消除利用相位变化的现有技术的存储单元中的大的单元表面积的问题。 通过本发明实现了具有比现有技术的DRAM器件更小的表面积的存储单元。 除了读取操作中的低功耗之外，本发明还提供即使在写入操作期间具有低功耗的相变存储器。 相变存储器也具有稳定的读出操作。
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公开(公告)号：US07324372B2
公开(公告)日：2008-01-29
申请号：US11507576
申请日：2006-08-22
IPC分类号： G11C7/00
CPC分类号： H01L27/101 , G11C7/12 , G11C8/10 , G11C11/16 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1693 , G11C13/0004 , G11C13/0026 , G11C13/004 , G11C13/0069 , G11C2013/0042 , G11C2013/0054 , G11C2013/0078 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144
摘要： The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected word line conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.
摘要翻译： 本发明的目的是避免在由存储器单元组成的存储器阵列中驱动未选择的数据线，每个存储器单元在选择的字线上的所有存储单元中的选择晶体管时根据可变电阻使用存储元件和选择晶体管 进行。 为了实现该目的，提供了与数据线并行的源极线，布置用于等电位驱动两者的预充电电路和用于选择性地驱动源极线的电路。 由于该配置，仅在由行解码器选择的单元中创建电流路径，并且可以生成列解码器，并且可以生成读出信号。 因此，与常规型相比，可以实现诸如相变存储器的低功率，低噪声和更高度集成的非易失性存储器。
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公开(公告)号：US07286430B2
公开(公告)日：2007-10-23
申请号：US11409238
申请日：2006-04-24
申请人： Satoru Hanzawa , Takeshi Sakata
发明人： Satoru Hanzawa , Takeshi Sakata
IPC分类号： G11C7/02
CPC分类号： G11C29/787 , G11C7/14 , G11C11/1673 , G11C11/1693
摘要： A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.
摘要翻译： 虚拟单元包括：多个第一存储单元MC，用于存储多个字线WR0至WR7与多个第一数据线D 0至D 7之间的交点处的“1”或“0” 多个用于存储“1”或“0”的第一虚拟单元MCH，布置在字线WR0至WR7和第一虚拟数据线之间的交点处，以及多个第二虚拟单元MCL，用于存储“0” “，布置在字线WR0至WR7之间的交点处和第二伪数据线DD 1之间。
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公开(公告)号：US20060187720A1
公开(公告)日：2006-08-24
申请号：US11409238
申请日：2006-04-24
申请人： Satoru Hanzawa , Takeshi Sakata
发明人： Satoru Hanzawa , Takeshi Sakata
IPC分类号： G11C7/10
CPC分类号： G11C29/787 , G11C7/14 , G11C11/1673 , G11C11/1693
摘要： A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.
摘要翻译： 虚拟单元包括：多个第一存储单元MC，用于存储多个字线WR0至WR7与多个第一数据线D 0至D 7之间的交点处的“1”或“0” 多个用于存储“1”或“0”的第一虚拟单元MCH，布置在字线WR0至WR7和第一虚拟数据线之间的交点处，以及多个第二虚拟单元MCL，用于存储“0” “，布置在字线WR0至WR7之间的交点处和第二伪数据线DD 1之间。
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公开(公告)号：US07078273B2
公开(公告)日：2006-07-18
申请号：US10876461
申请日：2004-06-28
IPC分类号： H01L21/82
CPC分类号： H01L27/2454 , G11C13/0004 , G11C2213/79 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.
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公开(公告)号：US07054214B2
公开(公告)日：2006-05-30
申请号：US11009449
申请日：2004-12-13
申请人： Satoru Hanzawa , Takeshi Sakata
发明人： Satoru Hanzawa , Takeshi Sakata
IPC分类号： G11C7/02
CPC分类号： G11C29/787 , G11C7/14 , G11C11/1673 , G11C11/1693
摘要： A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.
摘要翻译： 虚拟单元包括：多个第一存储单元MC，用于存储多个字线WR0至WR7与多个第一数据线D 0至D 7之间的交点处的“1”或“0” 多个用于存储“1”或“0”的第一虚拟单元MCH，布置在字线WR0至WR7和第一虚拟数据线之间的交点处，以及多个第二虚拟单元MCL，用于存储“0” “，布置在字线WR0至WR7之间的交点处和第二伪数据线DD 1之间。
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公开(公告)号：US07054200B2
公开(公告)日：2006-05-30
申请号：US10602885
申请日：2003-06-25
申请人： Satoru Hanzawa , Takeshi Sakata
发明人： Satoru Hanzawa , Takeshi Sakata
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C11/4074 , G11C11/4085
摘要： A semiconductor device to output voltages at three levels to a word driver while alleviating the breakdown voltage in the MOS transistor. This invention is comprised of a breakdown-voltage reducing MOS transistor inserted in the word driver and two NMOS transistors to supply a read-out voltage to a word line. The word driver is moreover controlled by different voltage amplitudes on the main word lines and the common word lines.
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公开(公告)号：US20050219934A1
公开(公告)日：2005-10-06
申请号：US11126214
申请日：2005-05-11
申请人： Satoru Hanzawa , Takeshi Sakata
发明人： Satoru Hanzawa , Takeshi Sakata
IPC分类号： G11C8/08 , G11C11/4074 , G11C11/408 , G11C15/00
CPC分类号： G11C8/08 , G11C11/4074 , G11C11/4085
摘要： A semiconductor device to output voltages at three levels to a word driver while alleviating the breakdown voltage in the MOS transistor. This invention is comprised of a breakdown-voltage reducing MOS transistor inserted in the word driver and two NMOS transistors to supply a read-out voltage to a word line. The word driver is moreover controlled by different voltage amplitudes on the main word lines and the common word lines.
摘要翻译： 一种半导体器件，用于将三电平的电压输出到字驱动器，同时减轻MOS晶体管中的击穿电压。 本发明包括插入字驱动器中的击穿电压降低MOS晶体管和两个NMOS晶体管，以将读出电压提供给字线。 此外，字驱动器通过主字线和公用字线上的不同电压幅度进行控制。
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