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114 条记录 (耗时 0.037 秒)

    Semiconductor integrated circuit device
    1.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US07619911B2

    公开(公告)日：2009-11-17

    申请号：US10579911

    申请日：2003-11-21

    申请人： Satoru Hanzawa ,  Junji Shigeta ,  Shinichiro Kimura ,  Takeshi Sakata ,  Riichiro Takemura ,  Kazuhiko Kajigaya

    发明人： Satoru Hanzawa ,  Junji Shigeta ,  Shinichiro Kimura ,  Takeshi Sakata ,  Riichiro Takemura ,  Kazuhiko Kajigaya

    IPC分类号： G11C15/00

    CPC分类号： G11C15/04 ,  G11C15/043

    摘要： In a memory array structured of memory cells using a storage circuit STC and a comparator CP, either one electrode of a source electrode or a drain electrode of a transistor, whose gate electrode is connected to a search line, of a plurality of transistors structuring the comparator CP is connected to a match line HMLr precharged to a high voltage. Further, a match detector MDr is arranged on a match line LMLr precharged to a low voltage to discriminate a comparison signal voltage generated at the match line according to the comparison result of data. According to such memory array structure and operation, comparison operation can be performed at low power and at high speed while influence of search-line noise is avoided in a match line pair. Therefore, a low power content addressable memory which allows search operation at high speed can be realized.

    摘要翻译： 在使用存储电路STC和比较器CP的存储器单元构成的存储器阵列中，将栅电极连接到搜索线的晶体管的源电极或漏电极的一个电极，构成 比较器CP连接到预充电到高电压的匹配线HMLr。 此外，匹配检测器MDr布置在预充电到低电压的匹配线LMLr上，以根据数据的比较结果来识别在匹配线处产生的比较信号电压。 根据这种存储器阵列结构和操作，可以在低功率和高速度下执行比较操作，同时在匹配线对中避免搜索线噪声的影响。 因此，可以实现允许高速搜索操作的低功率内容可寻址存储器。

    Ternary content addressable memory with block encoding
    2.
    发明授权
    Ternary content addressable memory with block encoding 失效
    具有块编码的三元内容可寻址存储器

    公开(公告)号：US07505296B2

    公开(公告)日：2009-03-17

    申请号：US11877310

    申请日：2007-10-23

    申请人： Satoru Hanzawa ,  Takeshi Sakata ,  Kazuhiko Kajigaya

    发明人： Satoru Hanzawa ,  Takeshi Sakata ,  Kazuhiko Kajigaya

    IPC分类号： G11C15/00

    CPC分类号： G11C15/04 ,  G11C15/043

    摘要： The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value ‘1’; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.

    摘要翻译： 有效存储范围指定的IP地址，以减少必要条目的数量，从而提高TCAM的存储容量。 本发明的代表性手段是：存储信息（条目）和输入信息（比较信息或搜索关键字）是公共块码，使得任何位必须是逻辑值“1”; 匹配线是分层结构的，并且存储器单元被布置在多个子匹配线和多条搜索线的交叉点处; 此外，子匹配线分别通过子匹配检测器连接到主匹配线，并且主匹配检测器被布置在主匹配线上。

    Semiconductor device
    4.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US06862232B2

    公开(公告)日：2005-03-01

    申请号：US10726658

    申请日：2003-12-04

    申请人： Satoru Hanzawa ,  Takeshi Sakata

    发明人： Satoru Hanzawa ,  Takeshi Sakata

    IPC分类号： G11C11/15 ,  G11C5/00 ,  G11C7/00 ,  G11C11/00 ,  G11C11/16 ,  G11C11/34 ,  H01L27/22 ,  H01L31/0328

    CPC分类号： G11C29/787 ,  G11C7/14 ,  G11C11/1673 ,  G11C11/1693

    摘要： A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.

    摘要翻译： 虚拟单元包括多个用于存储“1”或“0”的第一存储单元MC，其布置在多个字线WR0至WR7与多个第一数据线D0至D7之间的交点处，多个第一 用于存储“1”或“0”的虚拟单元MCH，布置在字线WR0至WR7和第一虚拟数据线之间的交点处，以及多个第二虚拟单元MCL，用于存储“0” 字线WR0〜WR7与第二伪数据线DD1的交点。

    Semiconductor memory device equipped with dummy cells
    6.
    发明授权
    Semiconductor memory device equipped with dummy cells 失效
    装有虚拟电池的半导体存储器件

    公开(公告)号：US06512714B2

    公开(公告)日：2003-01-28

    申请号：US09942558

    申请日：2001-08-31

    申请人： Satoru Hanzawa ,  Takeshi Sakata

    发明人： Satoru Hanzawa ,  Takeshi Sakata

    IPC分类号： G11C702

    CPC分类号： G11C11/4099 ,  G11C7/14

    摘要： There are provided a reference voltage generating method used for reading out operation of a memory cell having amplification ability, and a dummy cell. The memory cell is composed of a read NMOS transistor, a write transistor, and a coupled-capacitance. The dummy cell is made such that two memory cells are connected in series. The dummy cell is arranged at the most far end of each of the data lines against the sense amplifier. A reference voltage is generated by making a difference in an amount of current flowing in each of the read NMOS transistors of the memory cell and the dummy cell. As a result, DRAM showing a higher speed, a higher integration and a lower electrical power as compared with those of the prior art device can be realized.

    摘要翻译： 提供了用于读出具有放大能力的存储单元的操作的参考电压产生方法和虚拟单元。 存储单元由读取NMOS晶体管，写入晶体管和耦合电容构成。 虚拟单元被制成使得两个存储单元串联连接。 每个数据线的最远端布置在相对于读出放大器的虚拟单元。 通过使存储单元的读取NMOS晶体管和虚设单元中的每一个中流动的电流量的差异来产生参考电压。 结果，可以实现与现有技术的装置相比显示更高速度，更高集成度和更低电力的DRAM。

    Semiconductor integrated circuit having a clock recovery circuit
    7.
    发明授权
    Semiconductor integrated circuit having a clock recovery circuit 有权
    具有时钟恢复电路的半导体集成电路

    公开(公告)号：US06281725B1

    公开(公告)日：2001-08-28

    申请号：US09337421

    申请日：1999-06-22

    申请人： Satoru Hanzawa ,  Takeshi Sakata ,  Katsutaka Kimura

    发明人： Satoru Hanzawa ,  Takeshi Sakata ,  Katsutaka Kimura

    IPC分类号： H03L700

    CPC分类号： H03K5/135 ,  H03K5/133 ,  H03L7/0814 ,  H03L7/0818 ,  H04L7/0008

    摘要： A clock recovery circuit is provided for use in a memory with a clock synchronized interface or the like, wherein an external clock is temporarily intercepted to shorten the lock-in time when an internal clock is to be generated from the external clock. The clock recovery circuit includes a delay circuit array, into which an external clock is inputted, for generating a plurality of reference clocks, a control circuit for comparing the phases of the external clock and of the plurality of reference clocks and detecting the number of delay stages of the delay circuits required for locking in, and latching circuit for holding the number of delay stages required for locking in. Once synchronism is detected and the number of delay stages required for locking in are held in the latching circuit, the generation of the internal clock can be resumed in a short period of time even if the supply of the external clock is temporarily suspended.

    摘要翻译： 提供了一种用于具有时钟同步接口等的存储器中的时钟恢复电路，其中暂时截取外部时钟以缩短当从外部时钟产生内部时钟时的锁定时间。时钟恢复 电路包括：输入外部时钟的延迟电路阵列，用于产生多个参考时钟;控制电路，用于比较外部时钟和多个参考时钟的相位，并且检测所述多个参考时钟的延迟级数 锁定所需的延迟电路和用于保持锁定所需的延迟级数的锁存电路。一旦检测到同步，锁定所需的延迟级数被保持在锁存电路中，则产生内部时钟可以 即使暂时停止外部时钟的供给，也可以在短时间内恢复。

    Phase control circuit, semiconductor device and semiconductor memory
    8.
    发明授权
    Phase control circuit, semiconductor device and semiconductor memory 有权

    公开(公告)号：US06222792B1

    公开(公告)日：2001-04-24

    申请号：US09666598

    申请日：2000-09-20

    申请人： Satoru Hanzawa ,  Takeshi Sakata ,  Osamu Nagashima

    发明人： Satoru Hanzawa ,  Takeshi Sakata ,  Osamu Nagashima

    IPC分类号： G11C800

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222

    摘要： A phase control circuit comprises a plurality of fixed delay circuits (200-0 through 200-5) which assign different predetermined delay times to a first clock signal (BDA1) respectively, a detection circuit (201) which receives clock signals outputted from the plurality of fixed delay circuits and a second clock signal (PCLK) different in phase from the first clock signal therein and generates detected signals (202) represented in a plurality of bits each corresponding to the difference in phase between the first clock signal and the second clock signal, and a variable delay circuit (200-6) which gives a delay in the phase difference corresponding to each of the detected signals to a third clock signal (BDA2).